Going back several decades, Electrostatic Discharge (ESD) design and layout checks that were done manually were laborious and time-consuming, let alone not confidently reliable. These issues have been exacerbated by more advanced technologies along with the introduction of System on Chip (SoC) with digital, analog, and RF domains interacting. Thus, the complexity of ESD design verification needed sophisticated tools to bring in efficiency.
Nowadays, Electronic Design Automation (EDA) tools are particularly good at performing a considerable number of verification tasks in a very short time for ESD robustness and efficiency at both the schematic and layout levels on a broad spectrum of aspects. They brilliantly solve the well-known past issues of error-prone manual verifications. EDA tools’ flexibility allows one to employ them in every phase of the project design (from early debugging to final sign-off). They can be used directly by IC designers if a conscious usage is made. The involvement of ESD experts can be minimized during development.
The EDA checks can efficiently span a huge multitude of objects present in schematic and layout (components, circuits, nets, layers, properties) within a relatively short time. EDA tool precision can be tuned to obtain an advantageous tradeoff between accuracy and runtime. This is important to get complete verification results in time for a project design tape out.
Contemporary ESD EDA check tools can be divided into static and dynamic. The dynamic tools rely on electrical simulations of the ESD network, whereas the static tools rely on hard-coded rules predefined in runsets. Static checks are regarded as more reliable than dynamic checks for standard (general-purpose) architectures. Static checks are widely used in the industry and offered by many vendors and foundries.
The contemporary static-check tools constitute a flow that encompasses several aspects of ESD codesign, extracting information from schematics (circuit topology) and layout (resistance/current capability of metallization). If properly executed and defined, these checks can ensure high-quality ESD protection for projects with standardized architecture. In modern design packages, a clean output of ESD sign-off flow reassures successful ESD qualification of hardware.
EDA tools can be used as a safeguard for basic defined rules to avoid compromised ESD design mistakes. At the schematic level, the driver/receiver construction can be checked, including proper sizing, ballasting, or driver stacking. The existence and connection of primary ESD discharge paths via diodes, power, and local clamps can be reliably proven in schematics. Also, the placement and sizing of anti-parallel diode pairs between grounds can be easily checked using schematic-based topological checks. While this can still be managed manually in many cases, EDA tools help with sign-off automation. Furthermore, several advanced topologies can be detected by EDA schematic tools, e.g., vulnerable devices at signal cross domains (Figure 1).
The static-check tools executed on layouts can assess the hook-up resistance and current density for the typical ESD device in the discharge path providing advanced analysis capabilities (Figure 2). In complex ESD design cases involving large, distributed rail clamp networks, the EDA tools involving the layout can be used to simulate ESD events including the distributed metal bus resistance. These are static simulations. However, dynamic EDA checks are indispensable for special pads. A reliable dynamic checker could even be a competitive differentiator for the company.
While there are examples of commercial dynamic EDA tools, many large companies develop their own dynamic EDA tools and methods to secure competitive performance of, for example, high-speed interfaces with a tight capacitive load budget for ESD protection. Overall, one can state that the benefits of using EDA tools increase with the complexity of the ESD design.
In Part 2 of the article, we will discuss the limitations of EDA tools.
- Khazhinsky, et al, “Technical Report for ESD Electronic Design Automation,” ESDA Technical Report ESD TR18.0-01-14, 2014.
- Muhammad, R. Gauthier, J. Li, A. Ginawi, J. Montstream, S. Mitra, K. Chatty, A. Joshi, K. Henderson, N. Palmer, and B. Hulse, “An ESD Design Automation Framework and Tool Flow for Nanoscale CMOS Technologies,” Proceedings of 32nd EOS/ESD Symposium, pp. 1-6, 2010.
|Michael G. Khazhinsky is currently a Principal ESD engineer/designer at Silicon Labs in Austin, Texas.
|Eleonora Gevinti is a Senior Engineer in developing ESD EDA checks addressed to Smart Power BCD ICs at STMicroelectronics.
|Krzysztof Domanski a Principal Engineer in the field of ESD/Latchup on chip and system level at Intel.
|Guido Quax is part of the ESD team of NXP Semiconductors, focusing on high voltage ESD solutions, EDA tools, and (transient) latchup.
|Matthew Hogan is a Product Management Director for Calibre Design Solutions at Siemens Digital Industries Software.
|Founded in 1982, EOS/ESD Association, Inc. is a not for profit, professional organization, dedicated to education and furthering the technology Electrostatic Discharge (ESD) control and prevention. EOS/ESD Association, Inc. sponsors educational programs, develops ESD control and measurement standards, holds international technical symposiums, workshops, tutorials, and fosters the exchange of technical information among its members and others.