Ok, let’s start with the basics. What is latch-up, and why do designers care about it?
In today’s tightly packed layouts, most integrated circuits (ICs) end up with parasitic bipolar transistors (pnp and npn) somewhere. Latch-up is a short circuit, or low-impedance path, created by interaction between these transistors. Latch-up susceptibility can unnecessarily cause damage from electrical overstress (EOS) events. Unintended latch-up paths can lead to the risk of electrical damage or unexpectedly trigger during an electrostatic discharge (ESD) event. So checking for latch-up protection is now a mandatory verification requirement. Electronic design automation (EDA) tools already provide automated latch-up design rule checking (DRC) for 2D IC layouts. However, 2.5D/3D ICs present new and very different challenges when trying to apply these same rules with the same tools. It’s not impossible, but new latch-up verification flows are needed. That’s where my work focuses.
How do you protect against latch-up?
There are two key types of latch-up design rules—fundamental and advanced [1,2]. Fundamental (local) latch-up design rules focus on the physical dimensions of parasitic pnpn networks. Advanced latch-up design rules fall into two primary categories: external and mixed-voltage latch-up. External rules evaluate separation between an external injection source and victim circuit, so we have to be able to identify that injection source [3,4]. Mixed-voltage rules determine compliance by evaluating voltage difference, which can be critical in power sequencing operations [5,6]. In 2D ICs, we typically use manual markers to provide the required information. These markers are always subject to human error and are even harder to apply accurately in 2.5D/3D IC designs. My colleagues and I are focused on the development of automated latch-up physical verification flows for 2.5D/3D ICs that do away with markers entirely.
What makes 2.5D/3D IC latch-up verification different?
Actually, for fundamental rules, it’s not. 2.5/3D IC dies (Figure 1) are often designed on different technology nodes from different foundries. Consequently, local latch-up physical verification simply means applying appropriate local latch-up design rule checks (DRC) for every die separately.
2.5D/3D IC latch-up challenges come from the advanced latch-up design rules. In 2.5D/3D active dies, two types of off-chip interfaces exist: external IOs (communicate signals externally) and die-to-die IOs (communicate between active 2.5D/3D dies). Die-to-die IOs have no connection to package pins—they drive signals via micro-bumps, the interposer, and 3D traces. Automated latch-up checking must (1) recognize external IOs for every die from the assembly level, (2) identify external diffusions (latch-up injectors) inside every die topologically (external diffusion is connected to external IO directly or indirectly through resistors, diodes, switches,…etc.), (3) assign voltages to external IOs (or latch-up injectors) from the assembly level, and propagate these voltages to every die, (4) recognize that different dies have different advanced latch‑up rules.
We propose two automated flows: (1) a topology-aware flow for external latch-up design rules, and (2) a voltage-aware flow for mixed voltage latch-up design rules, both starting from the assembly level, and based on automatic differentiation between external IOs and internal IOs, without using any layout markers.
Why start at the assembly level?
The assembly level provides the complete picture of how the dies are connected with each other, so that’s where we differentiate between external and internal IOs. We assume internal IOs have low latch-up risk, so we perform appropriate latch-up verification on the external IOs only.
Layout cell-based extraction generates a layout netlist that describes the connections between dies, which we treat as black boxes. We identify external IOs and the port names of dies to which they connect at the assembly level, and generate a custom report for every die with its corresponding external IOs connections (Figure 2).
Then you move on to the specific checking flows?
Exactly. First, though, designers create latch-up constraints spreadsheets for every die with the relevant information needed to drive the die analysis, such as voltage values for external IOs (Figure 3). We get the external IO net names from the assembly-level custom reports.
The topology-aware latch-up flow addresses external latch-up design rules for every die. Latch-up injectors and corresponding layout geometries are automatically identified in this flow. We can then perform external latch-up DRC measurements on relevant geometries and report violations for debugging.
The voltage-aware latch-up flow addresses mixed-voltage latch-up design rules for every die. We propagate voltages through devices from defined external ports to internal nodes in the design, enabling identification of direct/indirect connectivity of latch-up injectors. Layout geometries of the identified latch-up injectors are captured automatically. We measure the relevant geometries for mixed-voltage latch-up DRC, and report violations for debugging.
Have you tested these flows in the real world?
We’ve tested our verification flows on a design with five dies: four random-access memory (RAM) dies and a controller die intentionally designed with external latch-up and mixed-voltage latch-up design rules errors (Figure 4).
The two flows correctly identified all expected latch-up conditions, enabling designers to quickly identify and apply the correct fixes. For example, connections between IOs of controller die and IOs of RAM die that don’t have any connections to the external world are considered internal IOs, so no latch-up risk is reported on them. Conversely, the flow correctly located P+ diffusions connected to external IO pads without proper protection, which the designers can correct by adding N+ guard rings.
Can you sum it up for us?
2.5D/3D IC verification can be challenging, but automated solutions like ours can not only reduce verification cycles but also improve the quality of the design. Our proposed flows provide a significant step forward by eliminating the need for manual markers and automating many of the verification steps. Implementing an automated latch-up verification solution for 2.5/3D IC designs ensures accurate and consistent latch-up protection, improving the reliability and product life of these products.
This article is derived from a paper presented at the 2020 EOS/ESD Symposium “Addressing Latch-up Verification Challenges of 2.5D/3D Technologies.” For a more detailed discussion of the processes and the flow evaluations, you can access the paper here: https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9241348.
References
- S. Voldman, Latchup. Hoboken, NJ: Wiley, 2007.
- S. H. Voldman, C. N. Perez and A. Watson, “Guard rings: Theory, experimental quantification, and design,” EOS/ESD Symposium, 2005.
- D. Alvarez, W. Hartung, and R. Bhandari, “ESD and Latch-up failures through triple-well in a 65nm CMOS technology,” EOS/ESD Symposium, 2018.
- T. Smedes, et al., “A DRC-based check tool for ESD layout verification,” EOS/ESD Symposium, 2009.
- M. Khazhinsky, et al., “EDA approaches in identifying latch-up risks,” EOS/ESD Symposium, 2016.
- A. Oberoi, M. Khazhinsky, J. Smith and B. Moore, “Latch-up characterization and checking of a 55 nm CMOS mixed voltage design,” EOS/ESD Symposium, 2012.
Founded in 1982, EOS/ESD Association, Inc. is a not for profit, professional organization, dedicated to education and furthering the technology Electrostatic Discharge (ESD) control and prevention. EOS/ESD Association, Inc. sponsors educational programs, develops ESD control and measurement standards, holds international technical symposiums, workshops, tutorials, and foster the exchange of technical information among its members and others.
