Mathew Yerian-French

Mathew Yerian-French is an electrical engineer specializing in EMC design and diagnostic testing. He received his B.S.E in Electrical Engineering from Grand Valley State University. He focuses on preventing EMC issues through design reviews and early EMC pre-compliance testing and diagnostics. Mat participates in the industrial collaboration with GVSU at the EMC Center.

From This Author

EMC Concepts Explained

Crosstalk Between PCB Traces – Time and Frequency Domain Measurements, Part 2

In this article, we investigate the impact of a guard trace on crosstalk reduction and present measurements taken with the latest‑generation PCB, both in time and frequency domains.

EMC Concepts Explained

Crosstalk between PCB Traces – Time and Frequency Domain Measurements, Part 1

This article is the first of a two-article series devoted to the topic of crosstalk between PCB traces. In Part 1 of the series, we vary circuit topology, i.e., the distance between traces and the distance to the ground plane.

EMC Concepts Explained

Impact of Decoupling Capacitors and Trace Length on Conducted Emissions in a CMOS Inverter Circuit

The authors evaluate the impact of capacitors and trace length on conducted emissions.

Columns

Impact of Decoupling Capacitors and Trace Length on Radiated Emissions in a CMOS Inverter Circuit

This article evaluates the impact of decoupling capacitors and trace length on radiated emissions.

Columns

Impact of a Decoupling Capacitor and Trace Length on Signal Integrity in a CMOS Inverter Circuit

This article describes a laboratory experiment that shows the impact of the decoupling capacitors and a PCB trace length on the signal integrity in a CMOS inverter circuit.

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Mathew Yerian-French

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What's New

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