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Souvic Mitra

Souvick Mitra is a Distinguished Member of Technical Staff in the Device Technology org in Micron Technology. His current mission is to drive his team to deliver ESD/LU protection development devices/solutions optimization for Micron's complete product portfolio covering DRAM, NAND and ASIC segments for various applications .He received his Master's degree from the Indian Institute of Technology, Kharagpur, in 1999, and the Ph.D. degree in electrical and computer engineering from George Mason University, Fairfax, VA, USA, in 2003. After completing his Ph.D., he joined IBM Semiconductor Research and Development Center and started working on the development of 90nm bulk compact models and led the 90nm low-power compact model activity. Prior to joining Micron, he was a Senior Manager-Deputy Director at GlobalFoundries, Essex Junction, VT, USA, managing a Global Team of ESD/LU engineers and before that, he was a Senior Engineer with IBM’s Systems and Technology Group. He has authored or coauthored more than 50 publications in journals and conferences and has been granted more than 100 patents.  His external involvement outside of Micron consists of serving as a Member, the Session Chair of Technical Program Committee, and a Moderator for EOS/ESD Symposium, International Reliability Symposium, and International SOI Conference for multiple years. He is currently serving as a Director at the ESD Association Board. He was the past Technical Program Chair and General Chair for 2020 and 2022 EOS/ESD Symposium, respectively.

From This Author

The Impact on ESD Risk of AI on Silicon Fabrication and the Implications of Increasing Memory Stacks

This column explores the significant impact of artificial intelligence on advancements in silicon fabrication, focusing on the development of high bandwidth memory (HBM) and associated die-to-die(D2D) electrostatic discharge (ESD) protection challenges.

What Are External Latch-up and Internal Latch-up?

Overall, latch-up prevention is one of the most important tasks for both foundries and IC designers. Based on the chip design scheme, designers should select proper solutions to eliminate the ILU and ELU risks in chip design, referencing the foundry guidelines and latch-up silicon data to ensure minimal latch-up risks for the product. 

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