Scott Mee

Scott Mee is a co-founder and owner at E3 Compliance which specializes in EMC & SIPI design, simulation, pre-compliance testing and diagnostics. He has published and presented numerous articles and papers on EMC. He is an iNARTE certified EMC Engineer and Master EMC Design Engineer. Scott participates in the industrial collaboration with GVSU at the EMC Center.

From This Author

EMC Concepts Explained

Impact of PCB Via and Trace Geometry on the Effectiveness of Decoupling Capacitors, Part 2

Conducted emissions testing on custom PCBs shows how moving a decoupling capacitor farther from an IC can increase emissions across multiple frequency bands. Using CISPR 25 methods, this study compares capacitor placements and via topologies to reveal how distance and inductance shape PDN behavior.
EMC Concepts Explained

Impact of PCB Via and Trace Geometry on the Effectiveness of Decoupling Capacitors, Part 1

Explore how PCB via and trace geometry influence the real‑world effectiveness of decoupling capacitors. This first article in the series defines six board variants, capacitor placement strategies, and PCB topologies, setting the stage for upcoming RF emission results based on CISPR 25 testing.
EMC Concepts Explained

EMC Education

Discover how a unique collaboration between Grand Valley State University and E3 Compliance creates exceptional learning opportunities in EMC and high-speed electronics. Learn how students gain hands-on industry experience through co-op programs, research projects, and real-world testing, preparing them for successful careers in electromagnetic compatibility.
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Return-Current Distribution in a PCB Microstrip Line Configuration, Part 2

This is the second article of a two-article series devoted to the return current distribution in a PCB microstrip line configuration.
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Return-Current Distribution in a PCB Microstrip Line Configuration, Part 1

This is the first article of a two-article series devoted to the return current distribution in a 2-layer FR-4 PCB microstrip line configuration with a solid reference plane.
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Evaluation of PCB Design Options on Analog Signal RF Immunity using a Multilayer PCB

This month’s column is the last of three parts devoted to designing, testing, and EMC immunity evaluation of multilayer PCBs containing analog circuitry.
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Evaluation of PCB Design Options on Analog Signal RF Immunity using a Multilayer PCB

This is the second of three articles devoted to the design, test, and EMC immunity evaluation of multilayer PCBs containing analog circuitry.
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Evaluation of PCB Design Options on Analog Signal RF Immunity Using a Multilayer PCB

This is the first of three articles devoted to the design, test, and electromagnetic compatibility (EMC) immunity evaluation of multilayer PCBs containing analog circuitry. In this study, there are seven design variants that all contain a similar schematic but implement different PCB layout techniques.
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Evaluation of EMC Emissions and Ground Techniques on 1- and 2-layer PCBs with Power Converters

This is the 10th and the final article in a series of articles devoted to the design, test, and EMC emissions evaluation of 1- and 2-layer PCBs that contain AC/DC and/or DC/DC converters and employ different ground techniques.
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Evaluation of EMC Emissions and Ground Techniques on 1- and 2-layer PCBs with Power Converters

We continue to focus on the AC/DC power converter board (2-layer PCB). We evaluate the implementation of several EMC countermeasures and present the conducted and radiated emissions results performed according to the CFR Title 47, Part 15, Subpart B, Class B.
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