Wei Liang

Wei Liang joined the GlobalFoundries ESD/latch‑up team in 2017 and has worked on latch-up mitigation and ESD protection development for advanced node technologies since then. Wei has authored or co-authored 16 peer-reviewed papers and holds three U.S. patents in the ESD area.

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What Are External Latch-up and Internal Latch-up?

Overall, latch-up prevention is one of the most important tasks for both foundries and IC designers. Based on the chip design scheme, designers should select proper solutions to eliminate the ILU and ELU risks in chip design, referencing the foundry guidelines and latch-up silicon data to ensure minimal latch-up risks for the product.

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