Guido Notermans

System level tests on a USB3 controller with on-board protection were found to yield irreproducible failure levels. A root cause analysis was performed using a combination of gun tests, TLP tests, and SEED simulation. It was found that an inductive current distribution between protection and SoC may explain the actual failure levels. Solutions are presented for effective on-board protection of USB3 controller boards.

It is no trivial matter to properly interpret system level test results on high-speed boards. Board manufacturers (OEMs) assess the ESD robustness of their system by means of gun testing, not always in accordance with the IEC standard.

Learn about the design of a stand-alone (off- chip) protection device which meets all requirements.