Why Tunnel FETs?

Past, Present and Future of Tunnel Field Effect Transistors: Part II

This month’s Hot Topics in ESD column is Part II of a two-part column. Part I appears in the May 2019 issue.

How Tunnel FET Works

Fundamental Principle

Figure 1 compares cross sectional view of a MOSFET and TFET. The only difference is in the way the source region is engineered, which in fact defines the carrier injection from source to channel. In principle a TFET is a gated p-i-n diode which behaves like a tunnel diode in ON state and like a reverse bias P-i-N diode under OFF state. Asymmetry in the structure and tunnel injection of carriers allows very high ION/IOFF; however, it restricts the source-drain exchange, which works well in case of MOSFET.

Figure 2 compares the operational difference between Tunnel FET and MOSFET. In case of MOSFET, carriers are injected thermionically over the barrier, whereas in case of TFET they are injected from source to channel due to gate field induced band to band tunnelling (BTBT). In the OFF state, alignment between the conduction band of the channel and the valence band of the source is missing, which avoids carrier tunnelling and maintains a very low leakage current. However, in the ON state, when the gate field is present, the channel region’s conduction band is pulled down, which allows it to align with the source region’s valance band. This alignment reduces the tunnelling barrier width and height, which allows carrier injection / tunnelling from source to channel region. This enables a sharp turn-on when the bands are aligned, and therefore allows TFET devices to operate well below the sub-thermionic limits with sub-threshold swing values below 60mV/dec. Under OFF state condition, TFET has comparatively higher barrier for the minority carriers, which leads to negligible leakage current due to minority carrier injection. In fact whatever leakage current exists in TFET is mostly dominated by SRH recombination and trap assisted tunnelling (TAT) [10] at the source-channel junction, which however, are well below leakage in MOSFET devices at shorter channel lengths.

Point TFET versus Area Scaled TFET

Despite its ability to combat short channel effects, enable voltage scaling and minimise leakage, the conventional/gated P-i-N TFET architectures suffer from their low ON current. In recent literature, this device is frequently referred as point TFET (Figure 3a). ON current of TFET is directly proportional to the tunnelling probability (T_BTBT) and tunnelling cross-section. The expression for the tunnelling probability obtained by approximating the tunnel barrier by a triangular barrier, as shown in Figure 4, and using WKB approximation is given by [12]:

Where m* is the effective tunnelling mass, Eg is the bandgap of the material, F is the electric field and  is the tunnelling distance.  For point TFET, the only parameter which one can engineer is to use the low bandgap material with low tunnelling effective mass. This improves the tunnelling probability and improves the ON current; which however is at the cost of increased SRH leakage. To keep the SRH leakage under control, use of low bandgap material only at the tunnel junction is a technique which is implemented widely. Except at the tunnelling junction (low bandgap source region for N-type device and low bandgap channel region for P-type device), rest of the device uses a relatively higher bandgap material, which is also known as hetero-junction TFET. Other methods which were proposed to improve point TFET’s performance were use of Low-k drain spacer, high-k source spacer, low drain doping, highly doped source, abrupt source junction profiles, post silicidation implant, and double gate architectures. However, they all suffer from extremely low ON currents, which is attributed to limited tunnel area available. This issue was addressed by increasing tunnelling cross section area, by introducing vertical tunnelling [1], [2] in the direction of gate field [8], [9] by incorporating a N-type pocket sandwiched between gate stack and P+ source (Figure 3b). This concept is also known as area scaled tunnelling [3], [4] or line tunnelling [5]–[7], which significantly improves the ON current, subthreshold slope and gate control over the tunnelling junction.

Pocket layer design and source engineering plays a very important role in line TFET’s performance. The design parameters are source and pocket layer’s doping and bandgap, as well as pocket region’s thickness [3]. One can say that the pocket engineering leverages additional control to design device for a range of applications. It is worth mentioning that line TFET architecture is CMOS compatible and easy to integrate using standard CMOS unit process steps [4].

TFET Future Beyond FinFET: Fin Enabled Area Scaled TFET

It took almost 20 years for FinFET technology to mature and become a reality for semiconductor products by replacing planar devices. However, as technology evolution doesn’t allow abrupt changes, FinFETs also enjoy advancements from planar nodes like High-k metal gate, raised/epi source-drain, strained silicon and gate last process. It is widely accepted that Si or SiGe FinFET can be replaced by TFETs, but what was not so clear was whether there will be a serious change in technological evolution while scaling below 7nm nodes. In other words how to take TFET concept to Fin-based technologies, allowing smooth transition from FinFET technology to Fin-based vertical Tunnel FETs, while enjoying benefits of FinFET architecture. To address this, a Fin Enable Area Scaled Tunnel FET namely ASF-TFET was recently proposed [10], as depicted in Figure 5. The working principle of this device is same as line TFETs, however the device enjoys excellent gate control over the channel as well as the tunnel junction, which improves the performance significantly [11] [13], as depicted in Figure 6. According to simulated results, ASF-TFET at 10nm gate length, when compared to the conventional vertical tunnelling FET or planar area scaled device, offers 100% improvement in ON current, 15× reduction in OFF current, 3× increase in the transconductance, 30% improvement in output resistance, 55% improvement in the unity gain frequency and more importantly 6× reduction in the footprint area for a given drive capability. Furthermore, the proposed device brings the average and minimum sub-threshold swing (SS) down to 40mV/dec and 11mV/dec at 10nm gate length. This gives a path for beyond FinFET System on Chip (SoC) applications while enjoying analog, digital and RF performance improvements [10].

TFET Beyond Conventional Semiconductors: 2D Material Based Hetero-Structure TFET

In recent years 2D materials like Graphene, Hexagonal Boron Nitride (h-BN) and Transition metal dichalcogenides (TMDC) have seen extensive investigations for electronics applications. These investigations revealed greater potential of 2D materials for low power SoC products, which is attributed to (i) their extraordinary channel properties, (ii) atomically thin channel, which allows excellent gate control and hence scalability beyond Si limits and (iii) flexible nature of 2D materials which allows integration over flexible substrates. Moreover, the 2D material surfaces are extremely flat and free of defects, which potentially offer improved device reliability. Like conventional semiconductors, various groups have been exploring TFET possibilities using 2D materials as well (Figure 7) [11]. Initial results depict a great potential of TMDC based tunnel FET, which is attributed to excellent gate control over the tunnel junction, scalability, broken gap TFET architecture and absence of TAT leakage; however, the technology still has a long road ahead, as far as meeting the semiconductor industry roadmap targets is concerned.

ESD Prospects

The ESD issues related to TFET devices are rather complicated to project at this time, which is due to TFET being not so matured technology having an evolving architecture. However, for a preliminary understanding of TFET ESD physics, readers can refer to the author’s recent publication [14].

References

1. K. Ganapathi, Y. Yoon, and S. Salahuddin, “Analysis of InAs vertical and lateral band-to-band tunneling transistors: Leveraging vertical tunneling for improved performance,” Appl. Phys. Letters, Vol. 97, No. 3, p. 033504, 2010.
2. L. Lattanzio, N. Dagtekin, L. De Michielis, and A. M. Ionescu,“On the static and dynamic behavior of the germanium electron-hole bilayer tunnel FET,” IEEE Trans. Electron Devices, Vol. 59, No. 11, pp. 2932–2938, Nov. 2012.
3. A. Rajoriya, M. Shrivastava, H. Gossner, T. Schulz, and V. R. Rao, “Sub 0.5 V operation of performance driven mobile systems based on area scaled tunnel FET devices,” IEEE Trans. Electron Devices, Vol. 60, No. 8, pp. 2626–2633, Aug. 2013.
4. R. Asra, M. Shrivastava, K. V. R. M. Murali, R. K. Pandey, H. Gossner, and V. Ramgopal Rao, “A tunnel FET for VDD scaling below 0.6 V with a CMOS-comparable performance,” IEEE Trans. Electron Devices, Vol. 58, No. 7, pp. 1855–1863, Jul. 2011.
5. A. M. Walke et al., “Fabrication and analysis of a Si/Si0.55Ge0.45 heterojunction line tunnel FET,” IEEE Trans. Electron Devices, Vol. 61, No. 3, pp. 707–715, Mar. 2014.
6. I. A. Fischer et al., “Silicon tunneling field-effect transistors with tunneling in line with the gate field,” IEEE Electron Device Letters, Vol. 34, No. 2, pp. 154–156, Feb. 2013.
7. K.-H. Kao et al., “Optimization of gate-on-source-only tunnel FETs with counter-doped pockets,” IEEE Trans. Electron Devices, Vol. 59, No. 8, pp. 2070–2077, Aug. 2012.
8. C. Hu et al., “Prospect of tunneling green transistor for 0.1V CMOS,” inProc. IEEE Int. Electron Devices Meeting, Dec. 2010, pp. 16.1.1–16.1.4.
9. R. Asra, K. V. Murali, and V. R. Rao, “A binary tunnel field effect transistor with a steep sub-threshold swing and increased on current,”Jpn. J. Appl. Phys., Vol. 49, No. 12R, p. 120203, 2010.
10. K. Hemanjaneyulu and M. Shrivastava, “Fin Enabled Area Scaled Tunnel FET,” in IEEE Transactions on Electron Devices, Vol. 62, No. 10, pp. 3184-3191, Oct. 2015.
11. Roy, Tania, Mahmut Tosun, Xi Cao, Hui Fang, Der-Hsien Lien, Peida Zhao, Yu-Ze Chen, Yu-Lun Chueh, Jing Guo, and Ali Javey, “Dual-Gated MoS2/WSe2 van der waals tunnel diodes and transistors,” ACS Nano Vol. 9, No. 2, 2015, pp. 2071-2079.
12. Sze, Simon Min,“Semiconductor devices: physics and technology”. John Wiley & Sons, 2008.
13. Qin Zhang, Wei Zhao and A. Seabaugh, “Low-subthreshold-swing tunnel transistors,” in IEEE Electron Device Letters, Vol. 27, No. 4, pp. 297-300, April 2006.
14. Kranthi Nagothu and Mayank Shrivastava, “On the ESD Behavior of Tunnel FET Devices”, IEEE Transactions on Electron Devices, Vol. 64, Issue: 1, Pages: 28 – 36, Jan. 2017. (DOI:10.1109/TED.2016.2630079)

Prof. Mayank Shrivastava received his PhD degree from Indian Institute of Technology Bombay. He is the recipient of two major international recognitions namely MIT TR35 award (2010) and IEEE EDS Early Career Award (2015). Beside these, he has received several national awards and honours namely 2018 Indian National Academy of Science (INSA) Medal for young scientists, 2017 Indian National Academy of Engineering (INAE) Young Engineer Award, 2018 INAE Innovator Entrepreneur Award, 2018 Indian Academy of Sciences (IASc) Young Associate award, 2018 National Academy of Sciences (NASI) Young scientist award, Excellence in PhD thesis award from IIT Bombay for his PhD research work in 2010 and 2008 IIT Bombay Industrial Impact Award. He has served in the TPC of more than 10 international conferences including IEDM, IRPS, EOSESD, etc.  Prof. Shrivastava’s current research deals with experimentation, design and modelling of beyond CMOS devices using Graphene and TMDCs, wide bandgap material based power semiconductor devices, high voltage devices in advanced CMOS nodes and ESD reliability in advanced and beyond CMOS technologies. He had held positions in Infineon Technologies, Munich, Germany; Infineon Technologies, East Fishkill, NY, USA; IBM Microelectronics, Burlington, VT, USA; Intel Mobile Communications, Hopewell Junction, NY, USA; and Intel Corp., Mobile and Communications Group, Munich, Germany. He joined Indian Institute of Science as a faculty member in year 2013. Prof. Shrivastava has over 100 international publications and more than 40 patents. More details related to his group or work can be found at: http://mayank.dese.iisc.ac.in.