What Are External Latch-up and Internal Latch-up?

What is a Latch-up Event?

As one of the major reliability concerns for the semiconductor industry, a latch-up event in bulk complementary metal-oxide-semiconductor (CMOS) technology originates from the base-collector coupled parasitic negative, positive, negative (NPN) (also known as sinking) and positive, negative, positive (PNP) (also known as sourcing) bipolar transistors.  The placement of the N-type and P-type devices in close proximity will result in the parasitic silicon-controlled rectifier (SCR) structure. Figure 1 and Figure 2 show the parasitic SCR structure in a CMOS inverter and the simplified parasitic SCR structure. When a latch-up event is triggered, a low resistance path forms between supply and ground, and a significant amount of current can flow through this parasitic path. This could, in most cases, lead to substantial chip damage when it is a sustained latch-up event that is being triggered. Holding voltage (Vh) is the minimum voltage required to keep the SCR structure at the on-state. A sustained latch-up event happens when the supply voltage (VDD) is higher than the Vh of the parasitic SCR structure because the VDD is high enough to keep the SCR turned on and won’t unlatch once it is triggered.

What Are Internal Latch-up and External Latch-up?

There are two main categories of latch-up, internal latch-up (ILU) and external latch-up (ELU). For the ILU event trigger, a few factors include the internal circuit creating supply bounce, on-chip transmission line reflections, or the on-chip generation of carriers. Those on-chip signals could trigger the parasitic SCRs formed in the bulk CMOS technology. However, for ELU, the parasitic SCRs are usually triggered by the off-chip signals received by the I/O signal pad. Those off-chip signals can create a large voltage bounce or carrier injection, triggering a latch-up event within an I/O block or in the weakest internal circuit adjacent to I/O cells. Figure 3 shows the negative mode of the ELU current injection from the I/O pad. The carrier injection flow paths are shown in the illustration.

How Does Technology Scaling Impact Latch-up?

As bulk technologies have scaled down to 5nm node based on the low-power requirement of the application, the VDD of the core circuit has been reduced to below 1.0 V. In applications with VDD < 1.0V, as Vh of the parasitic SCR structure is usually higher than VDD, there is no sustained latch-up and there are minimal ILU or ELU risks in this condition. However, the core circuit could work under overdrive mode, or the I/O circuit works under normal operating voltage where VDD > 1.0V occurs. In this condition, sustained latch-up could be a concern when Vh falls below the VDD, and proper ILU and ELU prevention guidelines should be considered.

How Do Foundry and IC Designers Address the Internal and External Latch-up Risks?

Since the latch-up event is a major reliability concern, the latch-up mitigation development becomes one of the most important tasks for the foundries to provide the IC designers with options to mitigate the latch-up risks in their design. The latch-up mitigation solutions are usually defined as a set of ILU and ELU ground rules in the technology process design kit (PDK) for the IC designers.

For ILU mitigation solutions, designers could either move the N-type device and P-type devices apart, increasing the anode to cathode spacing of the parasitic SCR structure, or add more well taps to reduce well tap spacing, reducing the parasitic well resistance, because larger well resistance could promote latch-up triggering.

To reduce the ELU risk, designers also have a few other options. Designers can either increase the distance between the injector and the victim device or increase the width of the guard ring which surrounds the injecting I/O cell. The wider the guard ring is, the more carriers will be contained within the I/O cell. Designers can also add a guard ring around the core circuit to reduce the amount of carrier reaching out to the victim device or reduce the well tape spacing in the core circuit to create a harder latch-up triggering condition. The overall design strategy to eliminate the ELU risk is a trade-off scenario for designers, and the solution should be customized based on the chip scheme.

Overall, latch-up prevention is one of the most important tasks for both foundries and IC designers. Based on the chip design scheme, designers should select proper solutions to eliminate the ILU and ELU risks in chip design, referencing the foundry guidelines and latch-up silicon data to ensure minimal latch-up risks for the product. 

Reference

  1. W. Liang, R. Gauthier, S. Mitra and H. Lai, “External latch-up Risks and Prevention Solutions in Advanced Bulk FinFET Technology,” 2019 41st Annual EOS/ESD Symposium (EOS/ESD), 2019, pp. 1-9, doi: 10.23919/EOS/ESD.2019.8869999.

About The Author

Wei Liang

Wei Liang joined the GlobalFoundries ESD/latch‑up team in 2017 and has worked on latch-up mitigation and ESD protection development for advanced node technologies since then. Wei has authored or co-authored 16 peer-reviewed papers and holds three U.S. patents in the ESD area.

Related Posts

Leave a Reply

Your email address will not be published.

X