For many applications, especially in digital designs, you can see decoupling networks composed of several different (big and small) capacitors in parallel. But, sometimes this technique can be dangerous.
Decoupling circuits is one of the most important techniques available to avoid EMI/EMC and signal/power integrity problems in your circuits , . This is a really complex subject, especially today when decoupling of circuits is not as easy as in the past because bandwidth (e.g. digital applications) goes up to hundreds of MHz or GHz.
For old technologies (below 30-50MHz in bandwidth), a simple capacitor has traditionally been an effective solution. A typical 100nF capacitor many engineers continue to use between VCC and GND in circuits is shown in Figure 1.
Supply voltage is VDC (e.g. 3V or 5V for a digital application) with output impedance Zs (e.g. output impedance of the voltage regulator). Layout of the power supply is added to Zs through parasitic inductance. Because device CKT requires transients of current (Iac) from that power supply network, three important effects appear (Figure 1, left):
- The loop of the layout can radiate or create crosstalk to nearby circuits (EMI problems);.
- Iac current harmonics circulating through your PCB board can create common mode impedance problems or can be radiated by cables connected to the PCB.
- Voltage drop in Zs and parasitic inductance because of Iac appear as a voltage drop ΔV = Ldi/dt for the CKT supply (signal/power integrity problems).
A capacitor close to CKT (Figure 1, right) solves those problems. Loop is reduced and Iac comes from the capacitor, not through the parasitic layout and power impedance. To be able to satisfy that function, the device CKT must see low impedance between power terminals (typically 0.2-1 ohms).
But real world capacitors have parasitic inductance (self resonant frequency specified by the manufacturer) and where/how the capacitor is placed will increase that inductance. The result is that, in high frequencies, the inductive effect increases the decoupling impedance.
To be able to minimize that impedance, a set of parallel capacitors (different values) is sometimes proposed. Big capacitors are intended to offer low impedance at low frequencies and small capacitors (higher resonant frequencies) are intended to offer low impedance in high frequencies. In Figure 2 you can see the theoretical idea using 4 capacitors (100uF, 10uF, 100nF, and 100pF).
But the ideal response we expect in Figure 2 offers sometimes an unexpected problem: a peak in impedance appears as you can see in Figure 3 for our four capacitors example.
Considering the RLC model for the capacitors, we can understand that effect as resonances between the paralleled components. In our example, we see a peak in impedance around 500MHz. At that frequency C0, C1 and C2 are inductive but C3 is still capacitive (see Figure 2). The parallel resonance creates that effect and the decoupling circuit will fail.
Note that the possibility for resonances to appear is dependent of the layout and parasitics and that high Q resonances will create severe peaks. A typical recommendation to avoid this problem is to use parallel capacitors with the same value (or not more than one decade in difference). Another possibility is to use a ferrite or small resistor between the resonant sections as in Figure 4 to add damping. Be careful with dissipation when using resistors and check for saturation limits when using ferrites.
As usual, considering these ideas at the design stage is the recommended strategy. My recommendation is to simulate and measure your power supply system to find resonances at the design and prototype levels.
- Henry W. Ott, Electromagnetic Compatibility Engineering, Wiley, 2009.
- Eric Bogatin, Signal and Power Integrity: Simplified, Prentice Hall, 2009.
Arturo Mediano received his M.Sc. (1990) and his Ph. D. (1997) in Electrical Engineering from University of Zaragoza (Spain), where he has held a teaching professorship in EMI/EMC/RF/SI from 1992. From 1990, he has been involved in R&D projects in EMI/EMC/SI/RF fields for communications, industry and scientific/medical applications with a solid experience in training, consultancy and troubleshooting for companies in Spain, USA, Switzerland, France, UK, Italy, Belgium, Germany, Canada and The Netherlands. He is the founder of The HF-Magic Lab®, a specialized laboratory for design, diagnostic, troubleshooting, and training in the EMI/EMC/SI and RF fields at I3A (University of Zaragoza), and from 2011, he is instructor for Besser Associates (CA, USA) offering public and on site courses in EMI/EMC/SI/RF subjects through the USA, especially in Silicon Valley/San Francisco Bay Area. He is Senior Member of the IEEE, active member from 1999 (Chair 2013-2016) of the MTT-17 (HF/VHF/UHF) Technical Committee of the Microwave Theory and Techniques Society and member of the Electromagnetic Compatibility Society. Arturo can be reached at email@example.com. Web: www.cartoontronics.com.
Hi A. Mediano,
I have tried plotting the combined impedance of multiple parallel connected capacitors expecting a broadened low impedance over a larger bandwidth. However, I not able to get a plot as you have explained in this informative article. I have used a network analyzer PSM3750 (M/s. Newtons4th). Individual plots and combined plots using three capacitors (10uF, 1uF and 100nF) did not yield the expectation. Kindly comment on the way it is measured as described in your article.
The impedance should be measured on the CKT side of the capacitors, not on the source side, because this is interesting now.
When using 3ohm, the PS impedance rise above 3ohm BELOW 400MHz!
Dear Bertalan. Yes, you are rigth and that is what I plotted: the impedance as seen by the CKT block. I mean impedance from right to left considering the voltage source (left) is a short circuit). I will check the data you have included in your post. Thanks for your comment.