Updated Trends in Charge Device Model (CDM)

Charged device events are by far the leading cause of electrostatic discharge (ESD) damage in modern electronics manufacturing facilities. If an integrated circuit contacts a conducting surface at a different potential, there is a discharge of current. Due to very low inductance and low resistance the discharge is very fast, often less than a nano second, but the currents can be up to several amps. Integrated circuits are required to have a certain level of robustness against charged device events to make them manufacturable. Charged device event robustness is measured using the charged device model (CDM) described in ANSI/JEDEC/ESDA JS-002-2022 [1]. In February 2021 Charvaka Duvvury and Alan Righter published an article in In Compliance Magazine outlining trends in CDM target levels and CDM testing [2]. Since that time, the Industry Council on ESD Target Levels released Version 3 of their white paper “A Case for Lowering Component-level CDM ESD Specifications and Requirements” (WP2 Version 3) [3]. This article provides an update on the trends discussed in the Duvvury and Righter article with insight from WP2 Version 3.

In the early days of CDM testing for reliability and qualification, the passing levels for qualification were often in the 500 V to 1000 V range. In 2009 the Industry Council on ESD Target Levels published the first version of their CDM white paper (WP2 Version 1) “A Case for Lowering Component-level CDM ESD Specifications and Requirements” [4]. WP2 Version 1 recommended 250 V as a reasonable target for CDM passing levels. WP2 Version 1 included significant data showing that with 250 V CDM levels integrated circuits could be handled in a manufacturing facility with basic ESD control with high yields. WP2 Version 1 also discussed how requiring higher passing levels restricted the level of performance that integrated circuits could obtain due to design constraints. Higher CDM levels require larger ESD protection circuitry and larger circuitry results in larger capacitance which restricts the bandwidth of high-speed interfaces. Since the release of WP2 Version 1 250 V CDM levels have largely been adopted by the electronics industry and there has been no negative impact from the adoption of 250 V CDM qualification levels.

In May of 2021, the Industry Council updated White Paper 2 to Version 3 (WP2 Version 3) [3]. WP2 Version 3 recommended a more nuanced approach due to advances and trends in the electronics industry. The Council continued to recommend 250 V CDM levels for most integrated circuits. For ultra-high-speed interface pins, however, the Council proposed a 125 V CDM level with the caveat that making the passing level as close to 250 V CDM as possible while meeting performance goals would have benefits in manufacturing. Figure 1, based on a figure from WP2 Version 3, summarizes the Council’s recommendations for CDM target levels as well as illustrates the ESD control levels provided by ANSI/ESD S20.20 [5], or similar ESD control standards IEC 61340-5-1 [6] and JEDEC JESD625 [7] as well as the advanced ESD process assessment procedures provided in ANSI/ESD SP17.1 [8].

WP2 Version 3 also discussed trends that are happening in the electronics industry that are going to continue to push CDM levels lower, placing more burden on manufacturers to control ESD to even more stringent levels. The remainder of this article will discuss those trends and the challenges they present.

Advance Technologies AnD Ultra-High-Speed Interfaces

Advanced technologies in the 7 nm and below range have even smaller ESD design windows to create ESD robust products. The ESD design window is essentially the voltage between maximum operating voltage and the voltage that will create permanent damage even for a very brief stress. A reduced ESD design window requires ESD protection structures with lower resistance, but lower resistance invariably results in higher capacitance as structures get larger. This conflicts with the push for higher speed interfaces. 

High speed interfaces such as SerDes (Serializer/Deserializer) are pushing to higher and higher data rates such as 225 Gb/s. The maximum data rate versus capacitive loading from ESD protection circuitry is shown in Figure 2 as well as the CDM levels that can be obtained in the various data rate ranges. There is currently no way to design interfaces at such speeds and have 250 V CDM levels. 

Handling integrated circuits with such high-speed data pins will require extra care in a manufacturing environment. Integrated circuits with such high-speed interfaces should also be designed with the high-speed pins kept away from corners and edges of a package where they are most likely to experience charged device events.

2.5D and 3D Packages

Advanced packaging is presenting CDM challenges well beyond the 125 V CDM proposed for high-speed interface pins. 2.5D and 3D packages involve the stacking of integrated circuit dies within a package. The completed package will still require >125 V and 250 V CDM levels, but the interfaces between the dies in the package face their own CDM risks during manufacture. The die in 2.5D and 3D packages often have 10s to 100s of thousands of connections.

The density of interconnects restricts the area available for ESD protection elements resulting in even lower CDM robustness levels as illustrated in Figure 3. Copper micro bumps with pitches in the 40 µm to 10 mm range can only afford the area penalty which can deliver about 30 V or less of CDM robustness. Hybrid bonding, in which chips or wafers are bonded together with direct copper to copper connections, can be made with contact pitches well below 10 µm. With such fine pitches, the area available for ESD protection elements is reduced and it is only possible to provide CDM levels on the order of 5 V. Fortunately, these levels of factory control are only needed in a limited number of steps in a cleanroom environment, but the ESD control issues are extreme. 

CDM Testing

CDM testing is a challenge at low voltages. Given et. al. [9] have shown that at low voltage, the field induced CDM test method specified by JS‑002 [1] gives very poor reproducibility in the stress waveform due to variability in the air discharge. Unfortunately, there is an increased need for accurate CDM measurements at low voltages. WP2 Version 3 encourages designers of ultra-high-speed buffers which cannot reach 250 V CDM not to drop their design target all the way to 125 V but to come as close to 250 V CDM as much as possible. Having the ability to accurately measure CDM levels between 125 V and 250 V with 10 or 20 V accuracy is therefore critical. Measuring CDM levels in the 10s of volts for 2.5D and 3D interfaces with the current field induced CDM from JS-002 is impossible. Fortunately, there are new developing options. 

A modification of the field induced CDM has recently been introduced, Relay Pogo Contact CDM (RP‑CCDM) [10]. In this method a small relay is included in the pogo pin of a field induced CDM tester. The method has been found to produce in specification waveforms but with significantly reduced variability at low voltages. This method promises to produce more reliable test results in the 100 V to 250 V range. Unfortunately, it is not expected that RP-CCDM will provide reliable measurements in the 10s of volts needed for 2.5D and 3D packaging.

Two other methods have also shown promise for low voltage CDM testing, low impedance contact CDM (LI-CCDM) [11] and capacitively coupled TLP (CC-TLP) [12]. Both methods use variations of very fast transmission line pulse testing to stress integrated circuit pins in which the stress is initiated in a relay removing the variability of air discharge. Additionally, both methods produce stress waveforms very similar to a CDM waveform but have very well controlled waveforms to low voltages. The two methods have been discussed in an earlier In Compliance article [13]. The challenge, especially for the Joint JEDEC/ESDA CDM working group which is responsible for JS-002, is to translate these two stress methods into equivalent CDM voltages. This work is underway in the working group.

Regardless of what low voltage CDM test method is selected by the industry, it will also be impossible to stress all interfaces of a silicon die intended for 2.5D or 3D as is common practice for standard packages. Some form of statistical sampling of interfaces will be needed. Additionally, functional testing of individual die intended for 2.5D or 3D application is an issue and performing ATE test after CDM testing may not be possible without completing the full package integration. It may be necessary to perform inference tests on die-to-die interfaces on test chips and assume “correct by design” in actual products.

ESD Factory Control

Regardless of what is done in terms of on-chip ESD protection design ESD factory control engineers will increasingly need to apply advanced ESD controls in assembly areas which in the past only needed basic ESD control. This will require additional efforts in terms of process assessment in all areas of a factory in which products with CDM levels below 250 V CDM are handled. The further below 250 V CDM, the more challenging the effort will be. The methods described in ANSI/ESD SP17.1 will need to be employed by a wider range of ESD manufacturing facilities.

Summary

As long as integrated circuits migrate to new technologies and advances are made in packaging more integrated circuit dies into a single package, the CDM challenge is going to get harder. Circuit designers need to design for as high a CDM level as they can within the performance requirements of the product, factory ESD control experts will need to better understand the ESD risks in their processes and determine ways to maintain the lowest possible voltages, and ESD test engineers will need to develop test methods to accurately know the CDM robustness of the products being manufactured. 

References

1. ANSI/ESDA/JEDEC JS-002-2022 “For Electrostatic Discharge Sensitivity Testing Charged Device Model (CDM) Device Level,” Electrostatic Discharge Association (ESDA), Rome, NY and JEDEC Solid State Technology Association Arlington, VA, 2022.
2. C. Duvvury and A. Righter, “Evolution of Charged Device Model ESD Target Requirements,” In Compliance Magazine, March 2021.
3. “White Paper 2: A Case for Lowering Component-level CDM ESD Specifications and Requirements Version 3,” Industry Council on ESD Target Levels, May 2021.
4. “White Paper 2: A Case for Lowering Component-level CDM ESD Specifications and Requirements Version 1,” Industry Council on ESD Target Levels, 2009.
5. ANSI/ESD S20.20-2021, “For the Development of an Electrostatic Discharge Control Program for Protection of Electrical and Electronic Parts, Assemblies, and Equipment (Excluding Electrically Initiated Explosive Devices),” Electrostatic Discharge Association, Rome, NY.
6. IEC 61340-5-1:2016, “Protection of electronic devices from electrostatic phenomena – General requirements,” International Electrotechnical Commission, Geneva 20, Switzerland.
7. JESD625C, “Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices,” JEDEC Solid State Technology Association, Arlington, VA.
8. ANSI/ESD SP17.1-2020, “ESD Association Standard Practice for the Protection of Electrostatic Discharge Susceptible Items – Process Assessment Techniques,” Electrostatic Discharge Association, Rome, NY.
9. R. Given, M. Hernandez, and T. Meuse, “CDM2 – A new CDM test method for improved test repeatability and reproducibility,” EOS/ESD Symposium 2010.
10. M. Drallmeier, L. Zeitlhoefler, H. Yang, W. Huang, F. zur Nieden, and D. Pommerenke, “A Relay Discharged FICDM Method for Improved Repeatability,” EOS/ESD Symposium 2020.
11. N. Jack, and T. Maloney, “Low Impedance Contact CDM,” EOS/ESD Symposium 2015.
12. H. Wolf, H. Gieser, W. Stadler, W. Wilkening, “Capacitively Coupled Transmission Line Pulsing CC-TLP – A traceable and reproducible stress method in the CDM-domain,” EOS/ESD Symposium 2003.
13. R. Ashton, “Low Voltage Charged Device Model (CDM) Testing at a Crossroads,” In Compliance Magazine, May 2022.