This article explains the creation of a bounce diagram for a transmission line circuit (see [1] for transmission line reflections).

Consider the circuit shown in Figure 1.

When the switch closes the forward voltage wave travels toward the load and reaches it at *t = T* (T = one-way travel time). Since the line and the load are mismatched a reflection is created and travels back to the source, reaching it at *t = 2T (assuming zero rise-time)*. Since the line and the source are mismatched, another reflection is created which travels forward to the load reaching it at *t = 3T*.

This process theoretically continues indefinitely; practically, it continues until the steady-state voltages are reached at the source and at the load. A *bounce diagram* is a plot of the voltage (or current) at the source or the load (or any other location) after each reflection.

The experimental setup for reflection measurements is shown in Figure 2.

The initial voltage at the location *z = 0* is

This is shown in Figure 3.

The reflection coefficient at the load is

The initial voltage wave of *6V* travels to the load and reaches it at *t = T* creating a reflection

*V *– = Γ* _{L}V *+ = (0.4845)(6) = 2.907

*V*

The total voltage at the load (at *t = T*) is

*V _{L}* =

*V*+ +

*V*– = 6 + 2.907 = 8.907

*V*

This is shown in Figure 4.

Voltage reflected at the load (*V *–= 2.907 *V*) travels back to the source. The reflection coefficient at the source is

The re-reflected voltage at the source is

*V *-+ = Γ* _{S}V *– = (-0.2)(2.907) = -0.5814

*V*

The total voltage at the source at *t = 2T* is

*V _{S}* =

*V*+ +

*V*– +

*V*-+ = 6 + 2.907 – 0.5814 = 8.3256

*V*

This is shown in Figure 5.

The voltage reflected at the source (*V *-+ = -0.5814 *V*) travels toward the load where it will create another reflection which will travel toward the source. This process will continue until the steady-state is reached.

The bounce diagram showing the voltages at the source and the load after each reflection is shown in Figure 6.

Figure 7 shows the voltages at the source (*z = 0*) while the Figure 8 shows the voltage at the load (*z = L*) during the period 0 ≤ *t* < 8*T* .

It is apparent the source and load voltages eventually reach the steady state. Recall that a transmission line can be modeled as a sequence of in-line inductors and shunt capacitors (assuming a lossless line) [2], as shown in Figure 9.

Under dc conditions (steady-state when driven by a dc source) inductors act as short circuits and capacitors act as open circuits.

Thus in steady state the circuit in Figure 1 is equivalent to the circuit in Figure 10 where the transmission line is modeled as an ideal conductor.

The steady state value of the voltage at *z = 0* is the same as the value at *z = L* and can be obtained from the voltage divider as

Note that both the source and the load voltages converge to this value as the reflection process approaches a steady state.

References

- Adamczyk, B.,
*Transmission Line Reflections at a Resistive Load*, In Compliance Magazine, January 2017. - Adamczyk, B.
*Foundations of Electromagnetic Compatibility with Practical Applications*, Wiley, 2017.

**
Dr. Bogdan Adamczyk** is a professor and the director of the EMC Center at Grand Valley State University (http://www.gvsu.edu/emccenter) where he performs EMC precompliance testing for industry and develops EMC educational material. He is an iNARTE certified EMC Master Design Engineer, a founding member and the chair of the IEEE EMC West Michigan Chapter. Prof. Adamczyk is the author of the textbook “Foundations of Electromagnetic Compatibility with Practical Applications”

*(Wiley, 2017). He can be reached at adamczyb@gvsu.edu*

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