Transmission Line Pulse testing is the default method for characterizing the behavior of devices under ESD circumstances. This article will introduce the method and its differences with classical ESD qualification methods. The history of the standardization work for TLP will be summarized. After two examples of the application of TLP, an outlook towards future developments will be presented.
What is TLP?
Transmission Line Pulse (TLP) testing is a method to characterize the behavior of components and circuits under ESD stress conditions , . In contrast to classical component level Electrostatic Discharge (ESD) testing methods, like Human Body Model (HBM)  and Charged Device Model (CDM) , TLP provides more than a pass/fail result. It actually provides a quasi-static I-V characteristic that describes the behavior of the Device Under Test (DUT). It can be regarded as a pulsed I-V measurement, using pulses with duration, rise time and current levels that are relevant for ESD events.
The pulses are made by charging a transmission line (typically 50Ω) to a pre-determined voltage and subsequently discharging into the DUT. By recording the incident and reflected waves with an oscilloscope, the DUT response can be measured. From the data in a defined measurement window in the stable part of the pulse, a quasi-static I-V point can be determined. Figure 1 shows a drawing of a typical pulse shape.
By repeating this charge/discharge procedure for multiple charge levels, a complete characteristic is established. Typical pulse duration is 100 ns, while typical current values can go up to a few Amperes. Generally, after each TLP pulse a low current DC measurement will be done in order to establish whether the DUT has been damaged by the preceding pulse. If the result of the DC measurement changes this often is an indication of device damage.
History of TLP Standardization
Although the idea of using transmission lines to generate short electrical pulses already existed earlier, it was not until 1985 that it was first introduced as a means to study semiconductor devices under ESD conditions . Initially most semiconductor companies built their own TLP system, but in the early 1990’s the first commercially developed systems became available. By now more than 10 companies offer TLP equipment.
To bring some commonality in the applied methods the ESDA started a working group to develop standard TLP approaches. This led to the publication of a Standard Practice document (SP 5.5.1) in 2004 . After successful Round Robin testing the document was elevated to a Standard Test Method (STM 5.5.1) in 2008 .
In 1996, a new version of TLP with shorter pulse duration and shorter rise times was introduced: very fast TLP (VF-TLP) . In 2007, a Standard Practice document on VF-TLP (SP 5.5.2) was released and a Round Robin experiment was started some years later .
Several revisions of these documents have been made. The 2014 version of STM 5.5.1 was republished by the IEC as IEC 62615 . In order to be more effective, the ESDA working group decided it was better to maintain a single generic STM document covering all quasi-static forms of TLP. The results of the VF-TLP Round Robin showed the method yielded accurate and reproducible results and thus could be elevated to Standard Test Method . Work was started to develop the generic document, which led to the publication of a new version of STM 5.5.1 in 2016, now covering VF-TLP, TLP and long pulse TLP.
ESD Applications of TLP
The most common application of TLP is the characterization of devices to see how they behave during standard ESD stresses, like HBM. A typical example is the 100 ns TLP characterization of a grounded-gate NMOST (ggNMOST), one of the workhorses in the field of ESD protections. Figure 2 shows the resulting TLP characteristics in the standard format introduced in . This should be read as follows. The drawn red curve with symbols is the device I-V characteristic: TLP current (left y-axis) vs. TLP voltage (bottom x-axis). The red dashed curve is the development of the DC leakage current (top x-axis) vs. the TLP current (left y-axis). From this characteristics several important parameters, such as trigger voltage (Vt1), holding voltage (Vhold) and soft/hard failure current (Isoft, It2) can be derived.
This characteristic could not have been measured with regular DC curve trace equipment. The DUT would most likely not survive the snapback when reaching the trigger voltage. If it would, the self-heating would be much stronger and the failure currents would much lower, because of the larger dissipation. Thus, the obtained values would not be realistic for the ESD regime.
Results as those in Figure 2, derived from 100 ns pulses with 10 ns rise time, describe the device behavior well for HBM-like events. A good rule of thumb is that 1 A TLP current corresponds to 2 kV HBM voltage, for dissipation driven failures . The correlation is not exact since TLP is based on square pulses and the HBM current is a decaying waveform with 150 ns time constant and waveform details may affect the device behavior. To understand the behavior for CDM-like circumstances much shorter and faster pulses are needed. Typically 1 ns pulses, with 100 ps rise time, are used. On the other hand, pulses longer than 100 ns may be more suitable for certain system level ESD events.
To get a more complete overview, characterization like explained above, can be repeated by TLP with different pulse widths. Each pulse duration will yield a different failure point (Vt2, It2). This implies that the power-to-failure will depend on the pulse duration. Collecting these points will give the boundary of the safe operation regime. An example is shown in Figure 3 . The Figure also shows that different regions can be distinguished, as explained by the Dwyer model . The power profile covers the ESD spectrum (CDM, HBM, System Level ESD) and even longer duration stress.
The examples above described the application of TLP on ESD protection devices (stand-alone elements). Such information can be used to design protection networks for ICs. It is also possible to perform TLP measurements on the circuit level, e.g. for debugging ESD qualification problems . However, the interpretation of the obtained characteristics is often more complicated, as in general multiple current paths exist between the connected terminals.
With applications like those sketched above, TLP has established a definite position as the indispensable characterization tool for ESD engineers. New TLP methods, options and applications are still being developed. TLP with different pulse shapes has been proposed  as an alternative to the so-called system level ESD gun (as described in IEC61000-4-2 ) for use in HMM . VF-TLP through a capacitor (CC-TLP) is proposed as an alternative for CDM, e.g. for small components that cannot be positioned in a regular CDM tester . Developments like these are expected to continue.
However, also with existing equipment, new applications are being explored. Apart from the quasi-static behavior presented in the above sections, also information about the transient turn-on behavior of ESD protection devices can be derived. Currently the ESDA working group is working on a document that describes the hardware requirements and procedures that are needed to extract parameters like turn-on time, voltage overshoot, etc. from the transient waveforms resulting from transmission line pulses.
In addition, the working group will release a TLP user guide in the form of a collection of application notes. These application notes are short guides on topics, such as correlation between TLP results and other ESD tests, use of TLP on wear-out testing, effects of de-embedding, etc.
Transmission Line Pulse testing is the de facto standard characterization and analysis tool for ESD circuit protection design. TLP can also be applied in some cases to verify the robustness of a protection device if unexpected HBM results are obtained during the standard ESD test. This feature of independent verification can be helpful during suspected ESD tester artifacts. However, caution must be used in such applications and TLP should not be used in general for product qualification.
In all cases, TLP is an indispensable method for describing the behavior of devices under ESD circumstances. Thirty years after its introduction into the semiconductors world, the application landscape is still growing. At the same time, improvements and extensions are developed and introduced.
- ANSI/ESD STM5.5.1, ESD Association Standard Test Method for Electrostatic Discharge (ESD) Sensitivity Testing – Transmission Line Pulse (TLP) – Component Level.
- JS-001, Joint JEDEC/ESDA Standard for Electrostatic Discharge Sensitivity Test – Human Body Model (HBM) – Component Level.
- JS-002, ESDA/JEDEC Joint Standard For Electrostatic Discharge Sensitivity Testing – Charged Device Model (CDM) – Device Level.
- T. Maloney and N. Khurana, “Transmission Line Pulsing Techniques for Circuit Modeling of ESD Phenomena” in Proceedings of the EOS/ESD Symposium, 1985, pp. 49–54.
- ANSI/ESD SP5.5.1, Electrostatic Discharge Sensitivity Testing – Transmission Line Pulse (TLP) – Component Level.
H. Gieser and M. Haunschild, “Very-fast transmission line pulsing of integrated structures and the charged device model” in Proceedings of the EOS/ESD Symposium, 1996, pp. 85–94.
- ANSI/ESD SP5.5.2, ESD Association Standard Practice for Electrostatic Discharge (ESD) Sensitivity Testing – Very Fast Transmission Line Pulse (VF-TLP) – Component Level.
- IEC 62615, Electrostatic discharge sensitivity testing – Transmission line pulse (TLP) – Component level.
- ESD TR5.5-03-14, ESD Association Technical Report for Electrostatic Discharge (ESD) Sensitivity Testing – Very Fast – Transmission Line Pulse (TLP) – Round Robin Analysis.
- J. Barth et al., “TLP Calibration, Correlation, Standards, and New Techniques,” in Proceedings of the EOS/ESD Symposium, 2000, pp. 85–96.
- G. Notermans et al., “Pitfalls When Correlating TLP, HBM, and MM Testing” in Proceedings of the EOS/ESD Symposium, 1998, pp. 170–176.
- T. Smedes et al., “Characterization Methods to replicate EOS Fails” in Proceedings of the EOS/ESD Symposium, 2014, pp. 384–392.
- V. M. Dwyer et al., “Thermal failure in semiconductor devices,” Solid State Electronics, 1990, Vol.33, pp. 553-560.
- T. Smedes et al., “Application of Transmission Line Pulse Testing for ESD Analysis of Integrated Circuits” in Proceedings EOS/ESD Symposium, 2001, pp. 426 – 434.
- E. Grund, “Snapback Device Studies Using Multilevel TLP and Multi-impedance TLP Testers” in Proceedings of the EOS/ESD Symposium, 2005, pp. 161–169.
- E. Grund et al., “Delivering IEC 61000-4-2 Current Pulses through Transmission Lines at 100 and 330 ohm System Impedances” in Proceedings of the EOS/ESD Symposium, 2008, pp. 132–141.
- IEC 61000-4-2, Electromagnetic compatibility (EMC) – Part 4-2: Testing and measurement techniques – Electrostatic discharge immunity test.
- ANSI/ESD SP5.6, ESD Association Standard Practice for Electrostatic Discharge Sensitivity Testing – Human Metal Model (HMM) – Component Level.
- H. Wolf et al., “Capacitively Coupled Transmission Line Pulsing CC-TLP – A Traceable and Reproducible Stress Method in the CDM-Domain” in Proceedings of the EOS/ESD Symposium, 2003, pp. 338–345.
Theo Smedes began work in ESD in 2000 and currently is Fellow for ESD, Latch-up and EOS within NXP Semiconductors. He published several papers on ESD and introduced an ESD design course within NXP. Theo is member of all ESDA device testing working groups and is chair of the TLP working group.
Founded in 1982, EOS/ESD Association, Inc. is a not for profit, professional organization, dedicated to education and furthering the technology Electrostatic Discharge (ESD) control and prevention. EOS/ESD Association, Inc. sponsors educational programs, develops ESD control and measurement standards, holds international technical symposiums, workshops, tutorials, and foster the exchange of technical information among its members and others.