You can minimize your EMI/EMC and SI/PI problems by working as slow as possible. This is very well known advice from many experts, books, and seminars: you can minimize or solve electromagnetic interference (emissions/susceptibility) and signal or power integrity problems working as slow as possible. But many times this strategy is ignored. Why is this idea so important?

When designing or analyzing any electronic product you can consider using the time and the frequency domains. And remember you can switch from one domain to the other.

You can calculate the frequency domain of your signal using the Fourier series (FS), the Discrete Fourier Transform (DFT) or the Fast Fourier Transform (FFT) depending on your signal, application, and your skills with math (the associate algorithms and equations are explained in any basic undergraduate course so it is not necessary to include that information in this article).

With the Fourier techniques you can consider that your signal is composed of infinite sinusoidal signals at different frequencies (i.e., harmonics). And, for that signal, as the frequencies increase in value, their amplitudes are smaller and smaller.

In Figure 1, the FTT of a square voltage signal (i.e., clock) is calculated with my scope. Odd and even harmonics are clearly shown, with decreasing amplitudes as the frequency value increases.

But, do you really need an infinite number of frequencies to represent your signal?

A practical answer is no. Usually, we can take a limited range of frequencies to represent our signals in real applications and this is what we call bandwidth. So bandwidth is, from a simple point of view, the maximum frequency in your signal.

Note that, from an EMI emissions point of view, as the bandwidth increases, the enclosures, wires, and PCB traces can act as efficient antennas easily.

From an EMI immunity point of view, as the bandwidth increases, your circuit will be able to respond to fast transients, so it is more susceptible.

From a Signal Integrity point of view, as the bandwidth increases, your connections (wires, PCB traces, etc.) can experience high frequency effects as reflections, crosstalk, and delays, easily affecting the integrity of your signals.

So, if you minimize the bandwidth of your signals, you will be reducing the probability to experiment with any of those problems. And how can you reduce the bandwidth of your signals? The answer for that question is inside the EFFT (Extremely Fast Fourier Transform), a very well-known tool included in many EMC publications.

Consider, for example, the spectrum for a random digital signal as shown in Figure 2. This is a 4.5V amplitude signal with nominal frequency f_{o }= 40MHz and 50% duty cycle (on time t_{ON }= 12.5ns).

But the important part for this signal is not in the nominal frequency. The important part is in the rise and fall times. Considering a rise and fall time of t_{R }= 2ns, we can draw the EFFT as the envelope of the amplitudes of harmonics in red color. The envelope is flat from low frequencies to corner frequency f_{1} = 1/πt_{ON }= 30.3MHz.

Then, amplitudes decrease at -20dB/dec.

At frequency f_{2} = 1/ πt_{R }= 159MHz, amplitudes decrease at -40dB/dec. We call that frequency the “knee frequency” and we consider the energy at higher frequencies has no important contribution to your signal. That limit can be considered and estimation of the bandwidth for your signal.

An equivalent idea can be applied to any periodic (i.e., clock) or non-periodic (i.e., ESD) signals, or to digital, analog, or power signals. And note that maximum frequency is related to the rise time so it is related to how fast the switching time is (clearly it is related with dv/dt and di/dt).

In Figure 3, a 5.78MHz digital clock is analyzed with two different rise and fall times. The fast signal (A) has a rise time of around 3ns. The slow version (B) has switching time of around 11ns.

Note in Figure 3 (right) how the bandwidth decreases when rise time increases (114MHz to 29MHz).

So, when your signal includes high frequency components because you are switching fast, you need to master all those high frequency techniques (layout, matching, etc.) typical of RF designers in the wireless business. Yes, you are right, you are a RF designer!

Obviously, if your system is a high-speed system, you will need to apply those special techniques and forget about working slow, but what about if you are working faster than needed?

So, remember the advice: work as slow as possible.

*Arturo Mediano** received his M.Sc. (1990) and his Ph. D. (1997) in Electrical Engineering from University of Zaragoza (Spain), where he has held a teaching professorship in EMI/EMC/RF/SI from 1992. From 1990, he has been involved in R&D projects in EMI/EMC/SI/RF fields for communications, industry and scientific/medical applications with a solid experience in training, consultancy and troubleshooting for companies in Spain, USA, Switzerland, France, UK, Italy, Belgium, Germany, Canada and The Netherlands. He is the founder of The HF-Magic Lab®, a specialized laboratory for design, diagnostic, troubleshooting, and training in the EMI/EMC/SI* and RF fields at I3A (University of Zaragoza), and from 2011, he is instructor for Besser Associates (CA, USA) offering public and on site courses in EMI/EMC/SI/RF subjects through the USA, especially in Silicon Valley/San Francisco Bay Area. He is Senior Member of the IEEE, active member from 1999 (Chair 2013-2016) of the MTT-17 (HF/VHF/UHF) Technical Committee of the Microwave Theory and Techniques Society and member of the Electromagnetic Compatibility Society. Arturo can be reached at a.mediano@ieee.org.

Dear Dave. First, sorry for my delay in sending a response.

If I understand your question, you mean the situation where signal is a switching waveform and you want to decrease the harmonic contents switching slower. Possibilities (not all possible I supposse):

1.- change to a slower technology (not possible from your question I think).

2.- add a slow driver in between

3.- add some kind of series element (usually a small resistor or a ferrite) as in the article. Usually the resistor must be small to avoid losses for your desired signal. Remember you want to increase switch time without excesive signal degradation. Usually ferrites with 50 to 120 ohms are a good option. You can see the idea in my article of September 2016 (www.incompliancemag.com/DigEd/icm1609/) where I explain aditionally some undesired (not usual) effects. The technique can be applied to a digital signal (i.e. clock), power electronics (the gate signal) if efficiency is not seriously degraded, etc. This is an effective solution in many cases.

4.- add a capacitor (usually pF). This capacitor avoids high dV/dt so high frequency harmonics are limited. Be carefull about signal integrity again so usually small caps are only possible. Sometimes in digital circuits, the capacitor can increase the transients in power supply current. Check about that if you detect an increase in emissions so you can improve the decoupling circuit.

5.- a combination of 3 and 4.

Please, let me know if I was able to answer your question. If not I will be glad to continue helping. Regards..-

So, when designing a system that runs slower than the latest generation components typically switch, how does one control rise/fall times or high frequency harmonics?