Two questions that often arise in and around engineering research and development cubicles, watercoolers, and office spaces are:

  • How does signal integrity (SI) compare to electromagnetic compatibility (EMC) and vice versa? and
  • Which of the two is the tougher design challenge (SI or EMC)?

The following article addresses these two very common questions involving two inter-related and specialized sub-fields within the realm of compliance engineering.

How Does SI Compare to EMC?

SI and EMC can be thought of as two different sides of the same coin, and there are some common design objectives between SI and EMC. However, a high-quality SI design does not automatically lead to a high-quality EMC design, and a high-quality EMC design cannot guarantee a high-quality SI design.

In short, SI is about maintaining signal quality from driver to receiver, and that crosstalk between two or more signals does not degrade the quality of the intended signal. SI involves ensuring timing margins are met, and signals do not exceed voltage thresholds that can damage or destroy both send and receive devices. There are no standards to be met, mandatory or otherwise. Just the requirement that the end-product function correctly in its intended application.

On the flip side, EMC is about properly designing products using rules of thumb and other well-established criteria to comply with governmental or market-driven emissions and immunity standards. EMC involves proper printed circuit board layout to limit the amount of unwanted common mode current allowed to flow out onto wires attached to the product. These currents are, in turn, measured by sophisticated test apparatus to determine if they fall under established limits. Recall that it only takes 5mA of common mode current flowing out onto wires to fail Class B radiated emissions limits.

Simulation is not that difficult or expensive in the SI world and is a very important part of developing products with good SI. Simulation brings several benefits, including reducing the risk of failure, enabling what-if analysis early in the design cycle, and providing information to justify design changes later in the design cycle, verifying their effectiveness, all while reducing time to market.

On the other hand, EMC simulation is currently not easy and currently not inexpensive. The best way to get the design right the first time is to design with EMC in mind and carefully layout circuit boards to achieve EMC. Early designs should be peer-reviewed before sending out for prototypes. It is best to obtain sample boards as soon as possible and test them using bench-top pre-compliance test methods or more official-like methods before attempting to pass official compliance tests.

Proper SI often involves the analysis and manipulation of what is found on the schematic, whereas proper EMC involves analysis and manipulation of the “hidden” schematic.

Basic Characteristics of SI versus EMC

Time Domain Frequency Domain
Voltage or Current Spectrum Voltage Waveform
Radiated or Conducted Not Relevant
High Threat Signals = Clock & I/O High Threat Signals = All High-Speed Signals
Common Mode Noise: Great Concern Common Mode Noise: Lesser Concern
Noise Levels of Concern = mA, mV Noise Levels of Concern = mA, mV
Low Pass Filters Widely Applied to All High Threat Signals Filters Judiciously Applied as Their Placement Can Negatively Impact SI Performance


Other SI vs. EMC Considerations

Several other design layouts may or may not negatively impact SI but will most likely affect EMC. As a minimum, these important EMC (but not SI) design criteria include:

  • Placement of high-threat clock/high-speed circuitry next to I/O circuitry;
  • Routing of clock traces away from the edge of the board;
  • Placement of I/O connectors on opposite sides of the board;
  • Placement of high-speed traces between the I/O connector and I/O circuitry;
  • Use of ground floods on signal layers;
  • Routing of clock traces on surface layers;
  • Use of decoupling capacitors;
  • Proper heatsink grounding;
  • Proper grounding of PCB mounting holes; and
  • Overlapping clock harmonics and use of spread-spectrum clocks…

… to name a few.

SI vs. EMC Considerations Based on a Signal’s Rise (Fall) Time or Frequency

Reference 1 states that for good SI, simulation techniques are recommended for all traces for which the bare-board tp ³ tr/10 or tr ³ 1/10πf (where tp is the signal propagation time, tr is the signal’s rise or fall-time [use whichever value is shorter of the two], and f is the highest frequency of concern. For good EMC, reference 1 recommends using simulation techniques when tp ³ tr/40 or tr ³ 1/40πf.


The above discussion addressed the first question posed at the beginning of the article:

“How does signal integrity (SI) compare to electromagnetic compatibility (EMC) and vice versa?”

To answer the second question:

“Which of the two is the tougher design challenge (SI or EMC)?

I would say that given the ever-decreasing rise-fall times that components are now switching at in present day and the increasing pressures put on design engineering to design and ship products in shorter development times, both are equally challenging. However, based on some of the above information, one could easily conclude that EMC is the tougher design challenge.

References and Further Reading

  1. Armstrong, K., EMC for Printed Circuit Boards, Armstrong/Nutwood UK, 2010.
  2. Bogatin, E., Signal and Power Integrity – Simplified, 2nd Edition, Prentice Hall, 2010.
  3. Syed, H., Relationship Between Signal Integrity and EMC, Selectron USA, Inc., RTP North Carolina, 2007.

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