This paper describes how to remove the measurement artifacts caused by discontinuities in high frequency S-parameter data caused by the test connectors on the Printed Circuit Boards (PCBs) and cables. The frequency domain S-parameters are converted to the time domain to get the impulse response. Time domain gating is then used on this impulse response to remove reflections due to end connectors and/or other discontinuities. The gated impulse response is then transformed back to the frequency domain. The final result is a much improved S-parameter data set with unwanted resonance removed, allowing the PCB trace or cable loss to be determined.
High speed data signals are significantly affected by the losses associated with printed circuit board (PCB) and cable conductor and dielectric material. Making direct measurements of this loss using a Vector Network Analyzer (VNA) is a common method to determine if the PCB trace and/or cable will cause an unacceptable amount of loss for the desired data rate and path length. However, the lengths associated with most PCB traces, and certainly with most cables, result in the likelihood of reflections and resonance effects in the S-parameter data when the cable or trace is not perfectly terminated in the characteristic impedance of the cable or trace. These resonances are length dependent, therefore the S-parameter results do not accurately indicate the true effects of the trace/cable, but rather indicate the loss associated with a particular length of trace/cable, and with the specific connectors used. Due to these measurement artifacts, the measurement results are often not useful for more general analysis of PCB traces (without connectors, but directly connected to an IC), or with cables that may use different connectors, or when the length of the trace/cable may vary. It is usually desired to have a measure of the trace/cable loss per unit length (per inch, meter, etc) so that the S-parameters for any required length can be created from the original measured data.
One option to remove unwanted connector effects is to use TRL (thru, reflect, line) VNA calibration. This VNA calibration method effectively removes these end effects by performing the calibration right on the PCB. However, this technique requires a number of different length traces on a PCB in order to calibrate over a wide frequency range. Also, the connectors themselves must be high quality connectors so their high frequency characteristics are all similar, as well as the dielectric material on the PCB must be consistent across the PCB. These requirements are not always possible, especially when using PCBs with low cost dielectric, and TRL does not apply for cables.
This paper shows a number of examples of the effects of time gating on PCB traces and cables. The agreement is very good, indicating that this procedure effectively removes the unwanted reflections/resonances and allows an accurate determination of the per-unit-length parameters for traces and cables.
Time domain gating is simply applying a windowing shape  to the time domain data, effectively weighting the time domain data and reducing the undesirable effects. There are many different windowing functions available: Rectangular, Hann(The Hann window is often called the “Hanning” window), Hamming, Blackman, Kaiser, and Cosine Squared are only a few of the more popular window functions. Each windowing function has an associated shape and is more or less complex to calculate. In general, the more complex (time consuming) that a given windowing function becomes, the better it reduces side lobes in the frequency domain. Figure 1 shows a few examples of the more popular window functions.
Figure 1: Examples of Hann, Hamming and Cosine Square Window Functions
By applying time domain gating (windowing) of frequency domain data, the effects of end connectors, etc. can be removed. The original frequency domain data (magnitude and phase) are transformed using an Inverse Fourier Transform to give a time domain impulse response. The time domain impulse response is then gated using a modified Hann window (The Hann window was selected due to its simplicity and good performance). The Hann window was modified to use the first half of the Hann window in Figure 1, but delayed until the start of the time domain pulse. This allows the high frequency portion of the impulse response to be maintained, while smoothing the late-time effects of the measurement artifacts.
The overall length of the gating window can be adjusted to remove unwanted end connector reflections. Once the gated impulse response is complete, the data are transformed back to the frequency domain. The length of the gating window determines the lowest valid frequency in the gated frequency domain data, and a low frequency correction using the original low frequency data, is required as the final step. This final step is important or the results below the lowest valid frequency will be incorrect. The resulting S-parameter data allow for a straightforward scaling to the desired length, since the end connector reflections/resonances have been removed.
Figure 2 shows an example of a PCB S21 measurement using SOLT calibration (ungated). Resonances cause obvious peaks and valleys in the S21 measurement above 2 GHz. These peaks and valleys can cause false signal integrity simulation results if the fundamental or harmonic frequencies of the signal fall into a peak or valley.
Figure 2: PCB Example of S21 Measurement
The ungated frequency domain signal was converted to the time domain using an inverse Fourier Transform. Figure 3 shows the resulting impulse response from the ungated signal in Figure 2.
Figure 3: Ungated Time Domain Impulse Response
After the main pulse in Figure 3, there are a number of reflections that can be seen. However, since Figure 3 is using a linear vertical scale, these reflections do not seem important. Since the scale in Figure 2 is a log scale, and the frequency range of interest has results as low as -60 dB, the time domain signal in Figure 3 is expanded in Figure 4. It is clear in Figure 4 that significant reflections occur.
Figure 4: Initial Time Domain Impulse Response (Expanded)
When a modified Hann window is used the time domain pulse is without significant reflections. The rectangular front edge of the window is set just before the rising edge of the impulse response. The tailing portion of the Hanning window is set to reduce the reflections after the main impulse. Figure 5 shows the gated impulse.
The gating operation removes low frequency information. This example used a 1 ns gate width; therefore, the gate is not wide enough to include the correct frequency domain data below 1 GHz. Low frequency S21 data is usually accurate, so the gated impulse is corrected by replacing the initial gated results with the original low frequency results (below 1 GHz in this example). The final gated-corrected impulse is also shown in Figure 5.
The impulse response is converted back to the frequency domain, and the final gated-corrected S21 data is shown in Figure 2. The gated-corrected data clearly has improved the S21 curve by eliminating the peaks and valleys in the original data.
A second example uses measured S-parameter data for a five meter long cable. Figure 6 shows the original S21 magnitude data. The effect of length related resonances/reflections is apparent below 1 GHz, and dominates the values above about 3 GHz.
Figure 6: Original S21 Data from Cable Example
The time domain original data, gated data, and corrected-gated data are shown in Figure 7. In this case, significant reflections occurred before the main impulse, as well as after it. The early reflections were due to a poor connection between the network analyzer and the differential cable. Due to the construction of the cable, it was impossible to improve this connection. This shows another important use for this time gating technique. If this ‘early time’ data is included in simulations, the results would be non-causal and incorrect. The final gated-corrected impulse is much cleaner than the original data. All the early reflection noise is eliminated, and nearly all the later reflection noise as well.
Figure 7: Time Domain Cable Results
The final frequency domain results are shown in Figure 8. The gate width was 3 ns, so the original frequency domain data below 333 MHz was used to correct the gated data at low frequencies. If Figure 6 and Figure 8 are compared, it is clear that the original data has been significantly improved by eliminating undesired resonance effects.
Figure 8: Final Frequency Domain S21 for Cable Example
Phase Errors in Measurements
In the course of making the measurements with the VNA we happened to measure the same cable with both a high frequency VNA (upper frequency at 20 GHz) and a low frequency VNA (upper frequency at 8 GHz). When the time domain impulse response was compared, The delay was different for the two different VNA measurements by a significant difference (Figure 9). The delay measured with the TDR was 42.8 ns matching the low frequency VNA. However, the high frequency VNA was reporting a much shorter delay for the same cable.
Figure 9: Time Domain Delay for Test Cable from Two Different VNAs
It was found that the high frequency VNA was set for 50 MHz steps. Figure 10 shows the original phase data before gating. The individual data points show that most of the phase wrapping for this cable was missed by the large frequency step size. This resulted in an incorrect and much lower phase delay (and hence less delay in the time domain) for the same cable. Once the frequency step size for the high frequency VNA was made small enough to capture the correct phase, the delay of the cable was the same for both VNAs.
Figure 10: Phase Information Missed by High Frequency VNA Due to Large Frequency Step Size
The final S21 magnitude once the gating and low frequency correction was performed is shown in Figure 11. The gated data without the low frequency correction is also shown.
Figure 11: Final S-parameter data for 10 meter Test Cable
While good measurement techniques and accurate calibration are extremely important, effects of reflections from imperfect signal launch (due to poor connectors and/or length resonances) can sometimes corrupt the desired data. This is especially true at high frequencies, at which the DUT becomes electrically long.
Even with careful calibration, the limitations of both the SOLT and TRL network analyzer calibration techniques often result in S-parameter data that is likely to give inaccurate results to signal integrity simulations.
The frequency domain S21 data were transformed into the time domain, and a modified Hann window was applied to data from both a PCB and a cable. Once the windowing was performed, the data were transformed back into the frequency domain.
The final S21 data were corrected for low frequencies by using the original low frequency S21 data.
The final S21 frequency domain data was clearly improved over the original data. End connector effects, and even a poor connection between the network analyzer, were eliminated using this gating procedure. Furthermore, care must be taken that the frequency step size is small enough so that phase information is not lost for long cables. This is usually not an issue for traces on a PCB since these traces tend to be short. Regardless of the path being measured, the issue of possible phase error in measurements must be considered and eliminated.
While not all network analyzer measurements require correction using gating, this procedure can extend the useful frequency range of simple SOLT calibration to higher frequencies than might otherwise be useful.
- Oppenheim, A. V. and Schafer, R. W., “Digital Signal Processing,” Englewood Cliffs, NJ: Prentice-Hall, 1975, pp. 241-250.
- Archambeault, B., Connor, S. and Diepenbrock, J.C., “Time domain gating of frequency domain S-parameter data to remove connector end effects for PCB and cable applications,” 2006 IEEE International Symposium on EMC, Volume 1, August 14-18, 2006, pp 199-202.
Dr. Bruce Archambeault is an IBM Distinguished Engineer at IBM in Research Triangle Park, NC and an IEEE Fellow. He received his B.S.E.E degree from the University of New Hampshire in 1977 and his M.S.E.E degree from Northeastern University in 1981. He received his Ph. D. from the University of New Hampshire in 1997. His doctoral research was in the area of computational electromagnetics applied to real-world EMC problems. He is the author of the book “PCB Design for Real-World EMI Control” and the lead author of the book titled “EMI/EMC Computational Modeling Handbook”.
Sam Connor is a senior engineer responsible for the development of EMC and SI analysis tools/applications. Mr. Connor’s current work activities and research interests also include electromagnetic modeling and simulation in support of power distribution and link path design for printed circuit boards. He has co-authored more than 20 papers in computational electromagnetics, mostly applied to decoupling and high-speed signaling issues in PCB designs. He is a Senior Member of the IEEE and is currently the webmaster for the TC-9 subcommittee of the IEEE EMC Society.
Joseph C. (Jay) Diepenbrock received the Sc. B. and M. S. degrees in electrical engineering from Brown University, Providence, RI, and Syracuse University, Syracuse, NY, respectively. Mr. Diepenbrock has worked in a number of areas in IBM including bipolar and CMOS IC design, analog and digital circuit design, backplane design and simulation, and network hardware and server product development. He is currently a Senior Technical Staff Member in the Interconnect Qualification Engineering department in IBM’s Integrated Supply Chain, working on the electrical testing and modeling of connectors and cables.