Return-Current Distribution in a PCB Microstrip Line Configuration, Part 1

Solid Reference Plane

This is the first article of a two-article series devoted to the return current distribution in a 2-layer FR-4 PCB microstrip line configuration with a solid reference plane. This topic was discussed in [1], where the analytical results for a solid reference plane were presented. In this article, we compare these analytical results to the CST Studio simulation results. Simulation results closely follow the analytical results and give an insight into the details of the return current distribution. In Part 2, we will discuss the return current distribution in the reference plane containing numerous via anti-pads (cutouts).

1. Relevant Background

In [2], the return path of high-frequency current was discussed for a two-layer PCB configuration shown in Figure 1.

Figure 1: Two-layer PCB with a solid reference plane

At points A and B, vias connect the top trace to the ground (reference) plane. The forward current flows on the top trace as shown in Figure 2.

Figure 2: Forward current flow

Upon reaching the point B the current travels to the reference plane and returns to the source (A). Current returns to the source through the path of least impedance. At high frequencies, the return current takes the path of least inductance, which is directly underneath the forward current trace, because this represents the smallest loop area (smallest inductance). This is shown in Figure 3 (not drawn to scale).

Figure 3: Path of the high-frequency return current

2. Return Current Distribution in the Reference Plane – Analytical Results

The microstrip line geometry is shown in Figure 4, where the trace of width w is at a height h above a reference plane; x is the distance from the center of the trace.

Figure 4: Microstrip line geometry

The current distribution in the reference plane underneath the trace is described by its current density [3], J(x):


where I is the total current flowing in the loop. This formula is valid at frequencies where the resistance of the reference return plane is negligible compared to its inductive reactance. This effect will be visualized in the simulation section of this article.

The current density underneath the center of the trace is:


Figure 5 shows the MATLAB plot of (normalized) current density underneath a trace as a function of x/h.

Figure 5: Current density underneath a microstrip trace

Note that most of the current tends to remain close to the area underneath the trace. As the distance from the center underneath the trace increases the current density becomes smaller.

3. Return Current Distribution in the Reference Plane – Simulation Results

Let’s verify the analytical results of the previous section through simulation. Figure 6 shows the CST Studio model of a two-layer PCB with a solid copper reference return plane and a microstrip trace on the top layer.  A source signal having an impedance of 50 ohms is used to excite the model.

Figure 6: CST Model – Two-layer PCB with solid reference return plane

Figure 7 shows the return current path (forward current trace is hidden) flowing in the reference plane at different frequencies.

Figure 7: Return current path at different frequencies

Observations: At 10 Hz the return current spreads wide over the reference plane, flowing both under the top trace and directly from the load port to the source port. As the frequency increases to 100 Hz, more of the return current flows under the trace (with a narrower spread), and less of it flows directly from the load port to the source port. This trend continues as the frequency increases to 1 kHz.

The results for 10 kHz and beyond show something very interesting. As the frequency increases beyond 10kHz, the return current path remains virtually unchanged, predominantly flowing beneath the forward trace. In other words, the return current path and current density no longer depend on frequency. The frequency is high enough that the resistance of the return plane is negligible compared to its inductive reactance, [3].

This phenomenon is explained in [4], as follows: “The current distribution, …, balances two opposing forces. Were the current more tightly drawn together, it would have higher inductance (a skinny wire has more inductance than a broad, flat one). Were the current spread farther apart from the signal trace, the total loop area between the outgoing and returning signal paths would increase, raising the inductance.”

Figure 8 shows the details of the PCB simulation model used to plot the current density distribution.  A straight line that cuts down the middle of the longitudinal axis of the reference plane is used to obtain the simulated magnitude of the current density.

Figure 8: Board geometry and the centerline location

Normalized current distributions at different frequencies along the z-axis are shown in Figure 9.

Figure 9: Normalized current distributions at different frequencies

When the frequency is above 10 kHz, the current distribution is virtually unaltered, i.e., does not depend on frequency, and predominantly remains underneath the forward trace. This is consistent with the result presented earlier in Figure 7.

The next article will discuss the return plane current distribution for a PCB with numerous via anti-pads (cutouts) in the reference plane, shown in Figure 10.

Figure 10: PCB with cutouts in the reference plane


  1. Bogdan Adamczyk, “PCB Current Distribution in a Microstrip Line,” In Compliance Magazine, November 2020.
  2. Bogdan Adamczyk and Jim Teune, “Alternative Paths of the Return Current,” In Compliance Magazine, May 2017.
  3. Henry W. Ott, Electromagnetic Compatibility Engineering, Wiley, 2009.
  4. Howard Johnson and Martin Graham, High‑Speed Digital Design, a Handbook of Black Magic, Prentice Hall, 1993.

Dr. Bogdan Adamczyk is professor and director of the EMC Center at Grand Valley State University ( where he regularly teaches EMC certificate courses for industry. He is an iNARTE certified EMC Master Design Engineer. Prof. Adamczyk is the author of the textbook “Foundations of Electromagnetic Compatibility with Practical Applications” (Wiley, 2017) and the upcoming textbook “Principles of Electromagnetic Compatibility with Laboratory Exercises” (Wiley). He can be reached at
Scott Mee is a co-founder and owner at E3 Compliance which specializes in EMC & SIPI design, simulation, pre-compliance testing and diagnostics. He has published and presented numerous articles and papers on EMC. He is an iNARTE certified EMC Engineer and Master EMC Design Engineer. Scott participates in the industrial collaboration with GVSU at the EMC Center.

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