Proposal for a Test Method to Assess the CDM Robustness of IP
An electronic device is susceptible to electrostatic discharge (ESD) damage during its entire life cycle, especially after the completion of the silicon wafer processing and until the device is assembled in the system. Wafer back-grinding, wafer-sawing, packaging, test, as well as board assembly and soldering, expose the device to ESD threats. To avoid yield loss due to ESD damage, extensive control measures are taken to maintain low electrical field levels in the device manufacturing. On the other hand, the device itself is protected against ESD with on-chip ESD protection networks which ensure ESD robustness for all exposed device pins.
ESD test models and simulators exist to assess the device’s ESD robustness. Most commonly used are the Human Body Model (HBM) and the Charged Device Model (CDM). HBM  simulates the discharge of a charged person touching a device, while CDM simulates a quick discharge of a charged device to ground.
Since its introduction in the 1990s, various CDM standards have been defined by JEDEC , ESDA , JEITA  and AEC . Recently ESDA and JEDEC released a joint standard ANSI/ESDA/JEDEC JS-002-2018 , which replaces the existing JEDEC and ESDA standards.
All CDM standards have in common a classification system based on voltage levels, see for instance the JS-002 classification in Table 1.
The discharge (peak) current, associated with a given CDM voltage level is not fixed but depends on characteristics of the device under test (DUT) like die size, pin count, package size and others. Consequently, if an interface IP block, e.g. the well-known USB, DDR, HDMI, MIPI, Ethernet, SATA interface, passes the CDM qualification for a certain voltage target on a test chip, there is no guarantee that this IP will pass the same voltage level when integrated on the product. For instance, if the product has a larger die or package size as compared to the IP qualification test chip, the CDM current at the same qualification voltage level on product can be higher and the IP might fail.
For this reason, it is for 3rd party IP providers by nature impossible to guarantee a CDM voltage specification for IP to be integrated in a yet unknown product; only a CDM peak current target should be used when the IP is qualified on test chip.
In the following section the principles of the CDM test method are described for understanding of the CDM discharge current dependency on the device. Next, the proposed CDM qualification procedure based on peak current is explained. Finally, we demonstrate how the customer can estimate the expected CDM voltage pass level of the IP in the product, using the IP’s CDM current specification.
Testing in a CDM Simulation Environment
In a CDM simulator equipment, the DUT is placed on an insulating fixture with the pins up (“dead-bug position”), as shown in Figure 1.
A high-voltage generator is used to set the potential on the field plate and charge the device to the desired voltage level, typically in the range of 125V to 1000V. Then the device is discharged through one of the device pins via a grounded pogo probe attached to a robotic arm. The procedure is repeated for positive and negative stress polarity and for each device pin successively. Next, parametric and functional tests are applied to determine whether the DUT was damaged.
As shown in Figure 2, the entire DUT consisting of the die, heat spreader, solder bumps, package pins/solder balls, substrate, etc. is charged. The total amount of CDM charge is a function of the device properties.
The maximum discharge current of the DUT is proportional to the total charge and therefore will be different for every device die and package characteristics. The discharge peak current at a certain CDM voltage setting will not be the same during the interface IP qualification phase compared to when the end-product is qualified.
When the charged DUT is grounded via one of its pins, the discharge current waveform is, amongst others, characterized by the current of the first peak (IPEAK), as shown in Figure 3.
Figure 4 illustrates how the CDM current depends on the device size. The CDM discharge peak current is measured for a large number of ball grid array (BGA) package types for 500V CDM stress as a function of the package size . Depending on the BGA package, the peak current for a 500V CDM discharge can vary from less than 4A to over 10A. The peak currents are proportional to the CDM voltage level, which means that for 250V the maximum peak current will typically not exceed 6A, as indicated by the blue line in Figure 4.
Peak Current as Design Parameter for On-chip ESD Network
The on-chip ESD network is part of the interface IP design and includes ESD devices such as diodes, clamps and interconnects (metal and contact layers) in the discharge paths. The primary parameter, determining the fail level of these ESD devices and interconnect, is the discharge current, so the CDM peak current is the leading ESD design parameter for the IP. The CDM voltage needed to achieve the peak current, is merely a derivative specification that can’t be determined without knowledge of the final device properties. The CDM voltage tolerance for the end product is not known in early development stages, when die and package properties are still unknown, leaving the CDM current as the only possible criterion to qualify the IP. For this reason, IP providers should use the CDM peak current target (ITARGET) for CDM design and qualification testing of their interface IP solutions.
Using Peak Current for Interface IP CDM Qualification
The proposed CDM qualification method for interface IP consists of two steps:
- Determine the correlation between CDM voltage (VCDM) and peak current (IPEAK)
- Execute the IP qualification at the target peak current (ITARGET)
Step 1: Determine the correlation between CDM voltage (VCDM) and peak current (IPEAK)
This step finds the CDM qualification voltage (VQUAL) of the DUT (in this case the IP test chip) that corresponds to the target qualification peak current (ITARGET). It is not critical which voltage levels are chosen for testing or whether the device passes or fails at certain CDM voltage levels. Good practice is, however, to have read-points below and above the target CDM voltage. The peak current to CDM voltage relationship is a linear function when the DUT is stressed at different CDM voltage levels, as shown in Figure 5.
To complete step 1:
- Stress all device pins (IOs and power/ground pins) at different CDM voltage levels;
- Monitor the discharge peak current waveform and determine the IPEAK for each pin;
- Calculate per CDM voltage level the average IPEAK of all stressed pins;
- Find the linear curve for CDM voltage vs. average peak current; and
- Use the ITARGET and the discharge current plot, see example in Figure 5, to determine the qualification CDM voltage (VQUAL).
Step 2: Verify the IP qualification at the target peak current (ITARGET)
To comply with the standards, three devices are used for the CDM qualification test. For this step the pass/fail data is crucial and determines the qualification results.
To complete step 2:
- Apply pre-stress parametric and functional pass/fail tests;
- Use VQUAL as voltage setting in the CDM tester;
- Stress all pins at VQUAL CDM level using three devices; and
- Apply post-stress parametric and functional pass/fail tests.
- The actual ITARGET is determined by the IP provider and should be aligned with the final product’s requirements. Note that a prerequisite for the IP qualification method is, that the test chip size is sufficiently large, so that the target peak current is reached at a CDM voltage below the practical limit
Assessing the IP CDM Performance in the Final Product
There are two options to estimate the IP CDM voltage level performance in the final product, based on the IP’s peak current qualification data:
- Use the correlation between CDM voltage and IPEAK of previous products in a similar package – the most convenient and accurate option;
- If option one isn’t attainable, estimate the expected peak current based on package size using IPEAK vs. package size relationship – shown in Figure 4.
Caution: Option #2 can only provide a coarse estimation since the construction of BGA packages can vary largely across different companies and the BGA peak current dependency in general may not follow the exactly same curve as the one from the referenced paper. Most accurate is to measure the peak current estimate on previous products in a similar package.
Questions & Answers
Q-1: I noticed that the human body model (HBM) specification of the IP is 1kV, a voltage specification like usual. Why do you keep voltage for HBM and change to current for CDM?
A-1: In case of HBM the actual discharge current at a given voltage (e.g. 1kV) is fully determined by the 100 pF / 1500 Ω in the HBM tester and practically independent of the chip and package properties. IP that passes 1kV HBM qualification on test chip will also pass 1kV HBM on the product (provided the IP has been correctly integrated on product). Since for CDM the current related to a given voltage stress level (e.g., 250V) can be very different on test chip and product, only with a (peak) current specification the test chip results can be projected on the product.
Q-2: My product has a CDM specification of 250V. The chip uses IP that is qualified for a peak current level of 6A CDM. How do I know whether the IP on my product will meet the 250V CDM target? The chip will be assembled in a BGA1156 package (35x35mm2).
A-2: Do you have a similar product using same BGA1156 package? If so, use that product to measure the discharge peak current at 250V CDM. Similar peak current can be expected for the new product, so if the peak current is less than 6A, the IP is expected to pass 250V.
If no previous product is available as reference, then use the properties of the product to estimate the average discharge peak current at 250V CDM. Make use of the graph of Figure 4 and check out the peak current at 250V for the applicable package size as indicated. For package area = 1225 mm2 and 250V CDM graph shows 4.8A, which is less than the IP qualification peak current of 6A.
Conclusion: By rough estimation, we assume that the IP in this product will pass the 250V CDM specification.
For CDM, the discharge current at a given voltage level is a function of many device properties, especially die and package size. Since the actual fail mechanism is determined by the discharge current rather than the voltage, the IP qualification fail levels measured on a test chip, respectively after integration in the product, will usually be quite different. This seriously reduces the value of IP qualifications with CDM voltage criterion.
To overcome this issue, we have introduced in this article a peak current criterion (e.g., 6A) for CDM qualification of IP. The CDM qualification data, together with basic properties of the final product, like the dimensions of the package, enables the user to determine whether the IP, when integrated on the product, is expected to pass the product’s CDM qualification class.
- ANSI/ESDA/JEDEC JS-001-2017, “Human Body Model (HBM) – Component Level,” May 2017
- JEDEC JESD22-C101F standard, “Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components,” October 2013, http://www.jedec.org
- EOS/ESD Association Inc., ANSI/ESD STM5.3.1-1999, “Charged Device Model (CDM) Component Level,” 1999
- JEITA CDM Standard, CDM (EIAJ ED-4701/300-2, Test Method 305A)
- Automotive Electronics Council, AEC-Q100-011 Rev-B, “Charged Device Model Electrostatic Discharge Test,” 2001
- ANSI/ESDA/JEDEC JS-002-2018, “Charged Device Model (CDM) – Device Level,” January x2019
- A. Jahanzeb, Y-Y. Lin, S. Marum, J. Schichl, C. Duvvury, “CDM Peak Current Variations and Impact upon CDM Performance Thresholds,” Proc. EOS/ESD Symposium 2007, pp. 283-288
Peter C. de Jong is an ESD/LU specialist at Synopsys, where he is responsible for the ESD solutions addressing a wide range of system interfaces. Prior to joining Synopsis, he spent 20 years at Philips Semiconductors Nijmegen (now NXP Semiconductors) where he worked on ESD protections for the company’s CMOS I/O libraries. de Jong holds an M.S. degree in Technical Physics from Delft University of Technology, and can be reached firstname.lastname@example.org.