What is 3D Integration and what is 3D IC?
If we rewind three decades, back in the 1980s, there were theoretical studies   which suggested that significant reductions in signal delay and power consumption could be achieved with 3D integrated circuits (3D ICs). A 3D IC is a chip that consists of multiple levels of thinned-active 2D integrated circuits (2D ICs) that are stacked, bonded, and electrically connected with vertical vias formed through silicon or oxide layers and whose placement within the levels is discretionary. As described in  such multiple levels could be the transferred layers of a 3D IC from design and physical layers and is the functional section of a chip or wafer that consists of the active silicon, the interconnect, and, for a silicon-on-oxide (SOI) wafer, the buried oxide (BOX). The basic features of a 3D IC are illustrated in Figure 1 in a symbolic drawing along with a cross-section of an actual 3D IC . The TSV (through silicon via) is an essential feature of the 3D IC technology and is the vertical-electrical connection (often known as pillars) formed between tiers and through silicon or oxide. A TSV is formed by aligning, defining, and etching a cavity between two tiers to expose an electrode in the lower tier; lining the sidewalls of the cavity with an insulator; and filling the cavity with metal or doped polysilicon to complete the connection. As noted in the 2015 ITRS Executive Summary , the use of the third dimension is one of the two main focus areas needed to continue the pace of progress for the semiconductor industry. This is commonly known as 3D integration.
Why 3D Integration?
3D Integration offers improved functional density for a given node along with performance boost and reduction in power requirements. “The potential benefits include higher performance, reduced power requirement, reduced latency, smaller size and eventually lower cost compared to 2.5D and conventional 2D packaging”, as stated in the ITRS document . Figure 2(a) from ITRS summary shows all the different driving forces that support the need of 3D integration. While in Figure 2(b), additional improvements like higher bandwidth/lower power, rapid access to memory, wide range of heterogeneous integration possibility, smaller Form-Factor etc., are shown.
3D Integration and ESD: What are the challenges
In an earlier ITRS Roadmap , ESD protection of the core logic devices is identified as a critical challenge for the 3D process sequence. Hence proper understanding of ESD protection levels is required for 3D integrated chip-to-chip signals with the goal of minimizing impact (area and latency) of 3D chip-to-chip connections. This understanding is required to determine optimal ESD protection design and associated ground rules required to handle any ESD event that occurs during the multi-step 3D/TSV integration process. The goal for ESD design is to protect against possible ESD exposure during assembly of various die into a 3D package. ESDA standard ANSI/ESD S20.20 provides a baseline ESD control system applicable to 3D assembly lines. This allows designing die-die I/O to meet 100V HBM while external I/O can be qualified to meet 200V CDM and 1000V HBM. To protect against ESD events during the 3D integration process, the designer needs to place ESD protection elements optimized for circuit performance and also area. Based on , such ESD protection elements can be placed inside the TSV Keep-Out-Zone (KOZ) to minimize the area impact. We also need to consider that per ITRS roadmap  shown in Table 1, TSV scaling will lead to smaller TSV pitch, which in turn will limit the Si area available to provide proper
|Min TSV Diameter||4-8µm||2-4µm|
|Min TSV Pitch||8-16µm||4-8µm|
|Min TSV Diameter||1-2µm||0.8-1.5µm|
|Min TSV Pitch||2-4µm||1.6-3.0µm|
Table 1: 3D-SIC/3D-SOC Roadmap
As shown in the flow chart in Figure 3, proper handling and caution are needed during backside thinning and die to die bonding, as these two are unique process steps in 3D integration. One needs to consider safe ESD path for CDM-like events during the integration process specifically for backside thinning . Based on , pre and post bonding measurements showed shift in leakage current when no ESD elements were used for the DUTs used for bonding, whereas for DUTs with optimal ESD protection elements showed no leakage shift before and after die bonding. This also means certain new aspects must be considered:
- Die planarity is critical to allow die to die bonding;
- Proper die orientation for multiple chips;
- is die padding required to match street sizes with die from different foundries;
- testability/quality of the various die in the package;
- is thin wafer handling required;
- a much more complex supply chain integrating more participants in the package integration process (i.e. extra die, interposer, etc.).
3D IC will bring increased packaging complexity and cost, but system performance will improve due to high speed interconnects over a shorter distance, leading to less power to be dissipated. With this increased complexity, the integrator would need an extensive checklist of requirements, matched against wafer fab, assembly, and test house capability. Further information on 3D IC effects on ESD design are documented in a white paper by the Global Semiconductor Association .
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- ITRS for Semiconductors 2.0, 2015 Edition, Executive Report
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- Chen S-H, Thijs S, Linten D, Scholz M, Hellings G, Groeseneken G, (2012) EOS/ESD Symposium proceedings ESD protection devices placed inside keep-out zone (KOZ) of through Silicon Via (TSV) in 3D stacked integrated circuits
- Mitra S; Gebreselasie E; Li Y; Gauthier R; Tran-Quinn T; Ramachandran K, (2016) IEEE Transactions on Device and Materials Reliability, 3-D Integration and ESD Protection: Design and Analysis, Vol 16, Issue: 4, pp 497 – 503
Souvick Mitra is a Principal Member of Technical Staff in Globalfoundries at Essex Junction, VT. His current research interests are in the area of ESD devices/solutions for advanced CMOS, FinFETs and beyond technology nodes. Prior to this position he was a Senior Engineer in IBM’s Systems and Technology Group. He completed his M. Tech in from Indian Institute of Technology, Kharagpur in 1999 and received PhD in Electrical and Computer Engineering from George Mason University, VA in 2003. After completing his PhD, he joined IBM Semiconductor Research and Development Center and started working on the development of 90nm bulk compact models and led the 90nm low-power compact model activity. After that he started leading ESD protection development and enablement for IBM’s analog and mixed signal, leading edge bulk CMOS , RF-CMOS, silicon-on-insulator (SOI) and research technologies (65nm-20nm). His external involvement outside of Globalfoundries consists of serving as member, session chair of technical program committee and moderator for EOS/ESD symposium, International Reliability Symposium and International SOI Conference for multiple years. He is also serving in the management/steering committee of EOS/ESD symposium and International ESD Workshop. He was the General Chair of 2016 International ESD Workshop held in Tutzing, Germany and Technical Chair of 2017 International ESD Workshop held in Lake Tahoe, USA. He has authored or co-authored more than 50 publications in journals and conferences and has granted over 70 patents.
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