HBM Pin Combinations

Question: I am beginning to do Human Body Model (HBM) electrostatic discharge (ESD) testing for my company, and every time I start testing a new integrated circuit I am faced with the same question. Should I use the pin combinations in Table 2A or Table 2B per HBM standard JS-001?

Answer: With apologies to Shakespeare; 2B or not 2B, that is the question [1], and it is a question that every HBM test engineer faces for every HBM test setup using the JS-001 [2] HBM standard. As with many things in life there is no “best” answer. It is a balance between engineering requirements, test time, and effort involved in setting up the test. I will begin by reviewing pin combinations in general, and then the differences between Table 2 A and Table 2 B.

In HBM testing of integrated circuits one or more pins are connected to Terminal B, considered a “nominal” ground, and a single pin is connected to Terminal A, as shown in Figure 1. A 100 pF capacitor is charged to the test voltage and then discharged through a 1500 Ohm resistor to the device under test. The pin(s) connected to Terminal B and the pin connected to Terminal A are a pin combination, and a full HBM test sequence is defined by stressing using all pin combinations defined in either Table 2A or Table 2B with both positive and negative stresses.


Figure 1: Basic HBM tester circuit


Figure 2 below combines Tables 2A and 2B from the HBM Standard JS-001, by showing the edits needed to change Table 2B to Table 2A. Table 2B defines the “Traditional” pin combinations from the original 2010 version of the JS-001 standard. JS-001-2010 used the same pin combinations as used in the JEDEC [3] and ESDA HBM [4] standards before those standards were merged into JS-001. The pin combinations in Table 2A were introduced in JS-001-2011. The intent of Table 2A is to reduce the number of individual pin combinations, and therefore reduce test time and device wear-out due to repeated stressing of the same circuit elements hundreds or thousands of times, while still stressing all meaningful HBM current paths.

Pin Combination Set Number Pin(s) Connected to Terminal B (Ground) Pin Connected to Terminal A
(Single pins, tested one at a time)
1 Supply Pin Group 1 Every Supply Pin Except pins of
Supply Pin Group 1
Every Non-Supply Pin
Associated with Supply Pin Group 1
2 Supply Pin Group 2 Every Supply Pin Except pins of Supply Pin Group 2
Every Non-Supply Pin
Associated with Supply Pin Group 2
N Supply Pin Group N Every Supply Pin Except pins of Supply Pin Group N
Every Non-Supply PinAssociated with Supply Pin Group N
N+1 One Pin of Each Coupled Non-Supply Pin Pair, one pair at a time
All Non-supply Pins, except Pin Under Test
The other pin of the Coupled Non-Supply Pin Pair
Each Non-Supply Pin (as the Pin Under Test)
Figure 2: Pin combination table showing edits needed to change the traditional Table 2B pin combinations to the updated pin combinations in Table 2A. (Notes present in JS-001 are not shown for clarity, but following the notes in the standard is important for proper testing.)


Two changes were made to reduce the number of pin combinations in Table 2A. The first involves the stressing of non-supply pins (inputs, output, IOs, and other pins that do not supply power) versus supply pin groups. In Table 2B, each non supply pin is stressed versus all supply pin groups. For example, in Figure 3, I1 would be stressed to VDD1, VSS1, VSS2 and VDD2 separately. In Table 2A stressing of non-supply pins is only done to supply pins “associated” with the non-supply pin in question.  Power supply groups that are associated with a non-supply pin are those that supply power to the buffer connected to the non-supply pin. In Figure 3, input I1 and output O1 are associated with power supply pin groups VDD1 and VSS1 and input I2 and output O2 are associated with supply pin groups VDD2 and VSS1. This reduction in pin count can be significant on large integrated circuits, which can have over two dozen separate power supply pin groups. This change to HBM pin combinations was first proposed by Gaertner et.al. in 2005 and was called the Partitioned HBM Test[5].


Figure 3: I1 and O2 are associated with VDD1 and VSS1 while I2 and O2 are associated with VDD2 and VSS2

The second update involves the stressing of non-supply pins versus other non-supply pins. In the traditional Table 2B each non-supply pin was stressed versus all other non-supply pins tied together, a test that was sometimes referred to as the “pin to the world test”. For example, in Figure 3 input I1 would be stressed on Terminal A versus O1, I2, and O2 tied together on Terminal B. This type of pin combination seldom resulted in failures and the current paths stressed were separately stressed with other pin combinations. In the rare cases where this pin combination produced unique failures the stress was hardly real world [6]. The pin to the world test was replaced by specifically stressing between “coupled non-supply” pins. Coupled non-supply pins are pins that share circuitry and typically work together, the best example being differential inputs or outputs. These types of pins are much more likely to have an ESD weakness than totally unrelated non-supply pins.

If you would like more information on the rationale behind Tables 2A and 2B, my blog on ESD testing issues,  https://minotaurlabs.com/blog/, includes posts on both pin combination tables.

Now, to truly address the question, which pin combination table to use? To answer this, we need to look at the advantages and disadvantages of each method. We will also assume that the testing is being done on an automated tester whose software generates the actual test sequence based on data input for each device pin.

Table 2A

  • Advantages
    • Shorter test times for complex integrated circuits
    • Less wear-out for complex integrated circuits
  • Disadvantages
    • Need more information about the device being tested
      • A datasheet or pin list is not enough
  • More time needed to setup the test program

Table 2B

  • Advantages
    • Don’t need as much information to setup test program
      • A datasheet or pin list is often all that is needed
    • Simpler test setup
  • Disadvantages
    • Longer test time
    • Possibility of false failures due to wear-out

From a test engineer’s point of view, Table 2B is easier. You don’t need to determine associated power supplies or identify coupled pins. Obtaining this information likely involves detailed discussions and email chains with product engineers and/or design engineers. The Table 2A or 2B question may be best framed as “Do I have a compelling reason to test using Table 2A?” The number of non-supply pins and the number of power supply pin groups is the most important question in determining how many fewer pin combinations there will be for Table 2A with respect to Table 2B. The number of pin combinations for non-supply to supply pin group testing can be determined with the following equations.

Comb2B = (number non-supply pins) X (number of supply pin domains)

Comb2A = (non-supply)1 X (supplies)1 + (non-supply)2 X (supplies)2 +…..+(non-supply)n X (supplies)n

where the subscript indicates groups of non-supply pins associated with specific power domains. If just two supplies, a VDD and a VSS, are associated with each group of non-supply pins the number of pin combinations reduces to.

Comb2A = (non-supply)1 X 2 + (non-supply)2 2 +…..+
(non-supply)n X 2 = (number non-supply pins) X 2

Interesting comparisons of the test times between the traditional Table 2B pin combinations and the Table 2A combinations are made by Brodback et al. [7].

If the difference between Table 2A and Table 2B testing is large the effort for Table 2A testing may be worth it, either for test time reduction or reducing the chance of wear-out. Additional reductions can be obtained with Table 2A by eliminating the pin to the world test and only stressing between coupled non-supply pins.

Another case in which Table 2A testing can be beneficial is if a multi power supply domain circuit fails when tested with Table 2B. If wear-out is suspected a retest using Table 2A may show that the device passes the HBM test when stressed a more reasonable number of times.

In summary, the choice between Tables 2A and 2B is largely practical, with the additional concern with regard to wear-out. Both do an excellent job of stressing the current paths that an HBM stress can take.

References

  • W. Shakespeare, “The Tragedy of Hamlet, Prince of Denmark”, Act III, Scene I.
  • ANSI/ESDA/JEDEC JS-001-2017 “For Electrostatic Discharge Sensitivity Testing Human Body Model (HBM) – Component Level”
  • JESD22-A114F “Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)”, JEDEC Solid State Technology Association, 2008.
  • ANSI/ESDA STM5.1-2007 “For Electrostatic Discharge Sensitivity Testing – Human Body Model (HBM) Component Level”, Electrostatic Discharge Association.
  • R. Gaertner et al., “Partitioned HBM Test –
    A New Method to Perform HBM Tests on Complex Devices”, EOS/ESD Symposium 2005.
  • Yen-Yi Lin et al., “Problems with IO to All Other IOs ESD Stress Test: Two Case Studies”,
    EOS/ESD Symposium 2005.
  • Tilo Brodbeck et al., “Statistical Pin Pair Combinations – A New Proposal for Device Level HBM Tests”, EOS/ESD Symposium 2008.


Robert Ashton
is the Chief Scientist at Minotaur Labs, www.minotaurlabs.com, a provider of ESD and latch-up testing located in Mesa, Arizona. He received his BS and PhD degrees in Physics from the University of Rhode Island. After Post-Doctoral positions at Rutgers University and Ohio State University he joined AT&T Bell Laboratories in the field of integrated circuit technology development. He stayed with Bell Laboratories, and its spinoffs Lucent Technologies and Agere Systems for 23 year where he became involved with on chip ESD protection. After leaving Agere Systems he became Director of Technology of White Mountain Labs, an ESD and latch-up test house. He then spent 10 years with ON Semiconductor in their discrete products division, providing and managing application engineering support for transient voltage suppression products. He has published numerous articles on ESD testing of integrated circuits, test structure use in integrated circuits, and CMOS technology development. He has also presented tutorials on ESD, latch-up, and transmission line pulse testing at IEEE and ESDA conferences. Robert is an active member of ESDA working groups for device testing standards and the JEDEC latch-up working group. He has been a regular member of the EOS/ESD Symposium technical program committee. Robert served on the ESDA board of directors from 2011 to 2013 and was business unit manager for advanced topics in 2012 and 2013. He is currently serving as vice chair of the human metal model (HMM) and System Level ESD Modeling working groups.

About The Author

EOS/ESD Association, Inc.

Founded in 1982, EOS/ESD Association, Inc. is a not for profit, professional organization, dedicated to education and furthering the technology Electrostatic Discharge (ESD) control and prevention. EOS/ESD Association, Inc. sponsors educational programs, develops ESD control and measurement standards, holds international technical symposiums, workshops, tutorials, and foster the exchange of technical information among its members and others.

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