ESD Parameters for ESD Design, IP Integration, and Verification

Electrostatic Discharge (ESD) protection of Integrated Circuits (ICs) requires seamless discharge paths and voltage clamping along the course of the discharge, between any pins combinations on the IC. The voltage built over the ESD shunting paths should be kept below the breakdown voltage of devices subjected to circuit nodes along the ESD current flow. This has to be guaranteed at the IC design level. As multiple parties are typically involved in the creation of an IC, effective interactions and ESD-related data exchange are essential to accomplish a successful ESD protection. ESDA working group 22 (WG22 – ESD parameters) has been formed to investigate and establish successful interactions and relevant exchange of information between the foundry IC suppliers, Intellectual Property (IP) vendors, and the IC designers. In addition, the use of Electronic Design Automation (EDA) tools for ESD protection verification has been considered, adding the EDA vendors to the classical IC manufacturing triumvirate.

WG22, chaired by Harald Gossner, published two technical reports. The first report, ‘Relevant ESD Foundry Parameters for Seamless ESD Design and Verification Flow’ (ESD TR22.0-01-14), was issued in 2014. The intent of the document was to serve as a guidance of best practice for extraction and provision of ESD-related parameters by the foundry, consolidating the efforts of the foundry, the IP vendors, IC design integration, and EDA vendors, ensuring IC ESD robustness. The following phase of the project, focused in the ESD perspective of an effective integration of Intellectual Property (IP) blocks in an IC, resulted in an additional document, ‘ESD Parameters from Intellectual Property Providers’ (ESD TR22.0-02-18), published in 2018.

Q: What are the motivation, scope, and content of the technical reports?

A: Partial information on HBM robustness, for example, of certain ESD structures or IO cells, is not sufficient to guarantee a successful IC level ESD protection. Furthermore, it is not feasible for foundries to cover all aspects of customer specific ESD solutions and related parameters, especially when they are not familiar with the ESD protection concepts, in an early phase of the technology development while the test structures for ESD are defined. ESD TR22.0-01-14 presents a generic set of ESD parameters and methodologies to extract them, focusing on a description of test structures and test procedures, as well as benchmark analysis and useful presentation of key charts and parameters.

In order to cope with the challenge of the electronic industry in development of highly complex System on Chip (SoC) products under extreme time and cost pressure, the use of IP macros provided by third-party vendors is a widely applied approach. Yet, in many cases, a lack of adequate information might make the integration of the IPs into an SoC ESD top-level design, extremely difficult. ESD TR22.0-02-18 addresses this demand by highlighting the ESD-related considerations relevant to IP selection, on-chip usage, and verification of correct integration. It describes technical parameters needed, as well as the required communication between IP vendors, SoC designers, EDA tools vendors, and the foundry. This document lists a generic set of ESD details which are applicable to most types of IP blocks. The variety of IP types are categorized by the different level of required ESD information. They range from various ESD ‘hardened’ IP blocks containing an ESD path like General Purpose I/O (GPIO) cells, through ‘soft’ (or protected) IPs like standard cells used in synthesized logic which might be subjected to the ESD path, finalizing with ‘unprotected’ IP blocks which are not exposed to the ESD shunt paths. TR22.0-02-18 describes the documentation and data exchange required to safely integrate the various IP blocks and effectively verify the ESD protection in the IC. In addition, it also gives an overview of the typical ESD-related integration rules to be provided depending on the IP data.

Q: What is the nature of the interactions between the parties involved in IC design, to ensure an ESD robust IC?

A: The interactions between the foundry, IP and EDA vendors, and the IC designers, for robust SoC design, are illustrated in Figure 1. Figure 2 depicts the typical activities and proposed best practices (detailed in the documents). The provision of ESD foundry process design kit (PDK) and ESD-related information enables appropriate choice of ESD protection by the IP providers, design of ESD robust IC, and verification of ESD protection by EDA checkers. All these enable optimal integration of IPs by the SoC designer as well as implementation check, resulting in an ESD robust product and short time to market.

TR22.0-01-14 describes the essential requirements of ESD-related technology data  from foundry suppliers needed by design customers, IP providers, and EDA tool vendors. This data contains the generic set of ESD parameters, including description of test structures and test procedures. TR22.0-02-18 highlights the ESD-related items  (Figure 2) relevant to IP selection, integration, on-chip usage, and verification with consolidated best practices between IP providers and users. The document provides a common understanding of key aspects for ESD robust third party IP selection and integration into a top level design. This is accomplished by describing the ESD related deliverables from the IP providers to be expected by the IP users and for ESD checks enablement by the EDA tool vendors. The specific expectations are detailed in the document. The exchanged information would also help in the debugging of the IP in case of ESD failures which might occur during SoC ESD qualification.

Figure 1: Foundry, IP provider, EDA vendor, and IC design interactions for ESD robust IC design


Figure 2: Typical activities and required interactions (detailed in the report) between the various stakeholders, to ensure ESD robust IC design

Q: Did the working group conclude its tasks?

A: WG22 has established, for the first time, technical documents focusing on ESD characterization and creation of relevant data, for better communication between the different parties involved in IC design and manufacturing. Though, there are additional challenges which should be faced. Among them are temporal effects, crucial in case of fast rise time / short duration stresses. This may involve vendors of testing tools as well. Another important aspect is system level ESD protection. The variety of complex mechanisms and possible threats, including residual stress forced onto the IC, requires new thinking about the necessary data. The current communication between the different parties, adding also the system integration, is not sufficient. This necessitates a discussion and generation of best practice procedures, failing criteria, and decision on required characterization and data extraction/exchange. Furthermore, Latch-Up robustness should be also taken into account as an important aspect of the analysis and practices. Last but not least, we should study and add new items featuring the continued technology scaling and new device configurations such as FinFET-based ESD devices, advanced isolation schemes, and 3D integration of ICs in package and system.


Both documents provide a common understanding of the ESD related deliverables between the foundry, IP providers, EDA tool vendors, and customers integrating foundry devices and third-party IPs into a top-level design. The ESD-related information exchanged between the parties, accelerates the integration and avoids misinterpretations leading to ESD fails. It improves the discussion between the customer and the foundry/IP provider and allows IP providers to prepare the required dataset upfront during the design and qualification of the IP block. Foundries benefit by the fact that a seamless IC design integration enables a faster ramp of the product to high volume. Given the growing complexity of SoC designs and IP delivery, these documents may constitute a significant stage in the pathway to efficient IC development and phase into production.


  1. ESD TR22.0-01-14, “ESD Foundry Parameters for Seamless ESD Design and Verification Flow,” EOS/ESD Association, Inc. 2014.
  2. ESD TR22.0-02-18, “ESD Parameters for Seamless ESD Design and Verification Flow – Part 2 – ESD Parameters from Intellectual Property (IP) Providers,” EOS/ESD Association, Inc. 2018.
  3. ESD TR18.0-01-11, “ESD Electronic Design Automation Checks,” EOS/ESD Association, Inc. 2011.

About The Author

Efraim Aharoni

Efraim Aharoni is a senior principal engineer at TowerJazz. He has led ESD and latch-up activities for the company worldwide, including the development of new ESD devices and protection concepts, ESD characterization and design guidelines. Efraim served in the Technical Committees of IEW and EOS/ESD symposium, is a co-chair of WG22 and a member in the Industry Council of ESD Standards.

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