ESD Open Forum

Updates to Past CDM Open Forum Questions

Q:  Does CDM have a defined Class Zero? (From 2007 Conformity Magazine issue, updated for 2018)

A:  The ANSI/ESDA/JEDEC CDM standard (ANSI/ESDA/JEDEC JS-002) has two ESDS “Class 0” CDM classification levels, C0b and C0a. This can be compared to the corresponding HBM standard (ANSI/ESDA/JEDEC JS-001) which breaks the Class 0 region into three regions (0B, 0A and 0Z). Table 1 shows these classifications and corresponding voltage ranges.

At this time there is not a “50 volt” region for CDM because of fundamental limitations of the current test method. The Joint ESDA/JEDEC Working Group on CDM is developing new test methods that will address this problem. A 50-volt CDM classification level is likely when these new methods are incorporated into the CDM standard.

CDM Classification Level CDM Classification Test Condition (in Volts)
C0a < 125
C0b 125 to < 250
HBM Classification Level HBM Classification Test Condition (in Volts)
0Z < 50
0A 50 to < 125
0B 125 to < 250

Table 1: CDM and HBM Class 0 classifications and voltage levels.

Q:  What is the ESD Association projected minimum withstand threshold for future electronic chips in terms of CDM? (From 2007 Conformity Magazine issue, updated for 2018)

A:  Advancing process technology, increasing package size / capacitance, and higher I/O speeds are all contributors to lower CDM I/O pin thresholds. This is because the necessarily smaller ESD protection feature sizes of the components, the circuit sizes and the chips result in reduced ESD threshold susceptibility.

The ESDA ESD Technology CDM roadmap ( in Figure 1 [1] shows the device ESD sensitivity trends from 2007 to 2020 for ESD models of HBM and CDM. The roadmap predicts for CDM by the year 2020 the lower CDM sensitivity level will be in the “TC 50” range. The need for improved CDM measurement accuracy at these very low levels is requiring new CDM test hardware to be developed (for example Low Impedance Contact CDM [2] and CC-TLP methods.

Figure 1: CDM Technology Roadmap through 2020 (showing necessary process specific measures to achieve the projected 100 and 50V CDM roadmap levels).



  1. Technology Roadmap from EOS/ESD Association,
  2. “Next Generation Charged Device Model ESD Testing” by Nathan Jack and the ESD Association, In Compliance Magazine, September 2017.


Founded in 1982, the ESD Association is a not for profit, professional organization directed by volunteers dedicated to furthering the technology and understanding of electrostatic discharge.  The Association sponsors educational programs, develops ESD Standards, holds an annual technical symposium, and fosters the exchange of technical information among its members and others.  Additional information may be obtained by contacting the ESD Association, 7900 Turin Rd., Bldg. 3 Rome, NY 13440-2069 USA, Phone 315-339-6937, Fax 315-339-6793.  Email,

Alan Righter is the 2018-2019 Senior Vice President of the EOS/ESD Association.  He is also ESDA co-chair (along with JEDEC co-chair Terry Welsher of Dangelmayer and Associates) of the ESDA/JEDEC CDM Joint Working Group responsible for developing the ANSI/ESDA/JEDEC JS-002 CDM Standard.  Alan is a Senior Staff ESD Engineer at Analog Devices, San Jose, CA.  He can be reached at

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