Managing the EMC Process So You Can Pass the First Time
Interpreting EMC Standards
Picture yourself as part of a team of engineers who are specialized in designing chargers. A new project comes along. How do you ensure the final design will pass the standard EMC tests the first time?
A typical first step is to interpret the relevant EMC standards that are applicable to the specific application. (Quality, safety, and environmental standards are equally if not more important, but they are not in the scope of this discussion.) One must look at the commercial EMC standards if the product is a fast charger for mobile phones and laptops. The automotive EMC standards should be applied if the product is an on-board charger (OBC) used in an electric vehicle. If it is a product based on wireless power transfer (WPT), one should refer to relevant standards and stay alert to changes as the standards are still being developed.
As an example, Table 1 lists the typical EMC test requirements that are applicable to an OBC.
|Radiated emission – Broadband sources
|ECE R10.6 Chapter 7.10 & Annex 7
|Radiofrequency disturbance voltages on AC or DC power lines
|ECE R10.6 Chapter 7.13 & Annex 19, average and quasi-peak detector IEC 61000-6-3
|ECE R10.6 Chapter 7.18 & Annex 9
|Transient disturbances conducted along 12V/24V supply lines
|ECE R10.6 Chapter 7.19 & Annex 10
|Fast transients – burst conducted along AC and DC power lines
|ECE R10.6 Chapter 7.15 & Annex 21
|Surge conducted along AC and DC power lines
|ECE R10.6 Chapter 7.16 & Annex 22
|Immunity to low frequency conducted disturbances – voltage dips and interruptions on AC supply lines
|IEC 61000-4-11 <16A per phase
IEC 61000-4-34 >16A per phase
|Immunity to electrostatic discharger
Table 1: Standards and regulations applicable to on-board charging systems
An Overview of the EMC Design Process
Once the requirements have been agreed upon by the design company and their customer, the design process follows. This design process typically follows a staged approach, as shown in Figure 1. It is highly recommended that the EMC design reviews should be performed at each stage of a product’s design and preliminary tests should be arranged as soon as the prototype of the PCB is ready. It is perhaps the only way to ensure strict EMC control to avoid major design changes at a later design stage.
In this article, we discuss how to implement EMC management during the design and development stage using practical demonstrations.
The Concept Stage
At the concept stage, engineers evaluate and select the topology of a charging converter based on the product requirements. It is essential to review the design with EMC in mind. A popular power converter topology for charging applications is a power factor correction (PFC) stage followed by a resonant circuit. Common PFC circuits include interleaved boost converters, bridgeless totem-pole converters, and interleaved totem-pole converters. Popular resonant circuits are an LLC, a phase-shifted full-bridge converter with current doubler rectifier, and so on. Figure 2 illustrates the converter topology of a 12 kW OBC (for demonstration purposes, only rail 1 of the converter is shown).
It is essential to have a PFC stage to improve the power factor of the grid and to achieve lower total harmonics distortion (THD) during the charging state. Without the PFC, charging, especially fast charging, draws a high peak current at the voltage peak and almost no current over the remaining mains cycle. This results in excessive high current flow in the mains conductors, the power transmission lines, and the power transformers.
In the example shown in Figure 3, an interleaved boost totem-pole PFC is selected because the two interleaved rails topology achieves halved current rating per half bridge. This results in ripple current cancellation on both the input and output of the PFC stage. As a result, this reduces the size of the bulk capacitor and lowers the EMC impact of the PFC. But this approach increases the number of switching devices and the complexity of the control. (Reference 1 offers a detailed comparison study between different PFC topologies but does not focus on the EMC performance analysis.)
It is the design engineer’s job to select the PFC topology based on the intended application. The decision needs to be based on the trade-offs between efficiency, ease of manufacturing, cost, weight, thermal considerations, and EMC. The topology also depends on the power rating of the applications. For instance, if it is a fast-charging device for a laptop or mobile phone, the PFC topology will be a simple boost PFC without interleaving. A number of trade-offs can also be seen when it comes to selecting the resonant converter stage. It should be noted that the zero-voltage switching (ZVS) has been widely used for resonant converters. When designed properly, ZVS provides significant circuit improvements in zero voltage switching and other areas, such as reducing common mode currents.
The Component Selection Stage
Reference 2 discusses the importance of selecting the right types of power electronics devices. For charging applications, choosing the right devices is essential to achieve a compact design and comply with EMC requirements. Among the devices of choice, wide bandgap devices such as gallium nitride (GaN) devices are widely seen in commercial applications such as fast chargers for laptops and phones, while silicon carbide (SiC) devices are dominant in the high voltage high power applications such as OBCs used in electric vehicles.
As shown in Figure 4, most GaN devices are surface-mounted with integrated driver circuits, while most SiCs are through-hole discrete devices because of the high-power level. Though D2PAK SiC devices are available, they are not a design engineer’s favorite choice, mainly because of the different thermal characteristics associated with the package.
Through-hole devices are robust, low cost, and enjoy better thermal characteristics, and are therefore widely used in high voltage, high power applications. But, for EMC, they are not as good as the surface-mounted devices because the extra-long leads of the package introduce larger inductance.2 Being physically tall, they also radiate more efficiently compared with surface-mounted devices. The thermal design around these devices is crucial as heatsinks are often much larger than the devices themselves. If the heatsink is not grounded well, it can radiate much more at a lower frequency range (30-300MHz).3
Apart from switching devices, magnetics components such as the transformer used in the resonant converter stage also need to be designed with EMC considerations in mind. System efficiency is always the most important design factor. Therefore, a transformer’s losses (including core losses, copper losses, skin effect, and proximity effect) are often given significant consideration during the design stage. The ZVS scheme also requires a saturable core of the transformer and prefers higher leakage inductance. This means that the EMC design of a transformer is often overlooked.
A simple electrostatic shield can often help reduce the common mode current when added to the transformer.4 The shield needs to be connected to 0V on the primary side and should be kept as thin as possible to minimize eddy current loss due to the proximity effect. A second shield on the secondary side improves the EMC performance further, but at extra manufacturing cost.
Other techniques in the transformer design include common mode current cancellation or the so-called common mode current balance based on a unique winding structure design.5 It should be noted that transformer design is also the key to optimizing the ZVS of the converter.
During the design review, pros and cons of each component selection should be assessed. Efficiency, size, and cost are often the key factors in selecting components. But the comparison should also account for EMC considerations as well. For example, engineers often select components so that the best form factor and minimum cost are achieved, only to find out that a heavy, bulky, and expensive filter needs to be added on at a later stage because the selected switches/transformer create too many EMI issues. If the issue had been highlighted early during the component selection stage, total time and cost could have been reduced.
The Schematic and Layout Review Stage
During the schematic review, attention should be paid to the following areas:
- The gate driver design should be reviewed, switching speed (rise time and fall time) of the switching devices should be analyzed based on the gate resistors, and risk analysis should be performed. The review should also extend to the bootstrap circuit for non-isolated gate drivers and snubber circuit design.
- Input and output filters are key to the EMC performance of a charger. The insertion loss of each filter stage should be calculated/simulated. The filters should be most effective in the frequency range between a few kHz to 100s of MHz.
- Decoupling capacitors are essential for all switched mode power supply designs. Design engineers should check if sufficient decoupling capacitors are placed in the key areas of interest. These key areas are power lines (primary and secondary sides), transformers (between primary and secondary), and connections to the chassis.
When it comes to the layout review, the devil is in the details. A layout review can easily cost a few days’ time with design engineers from multiple disciplines involved. Decoupling capacitors, filter locations, connectors, traces, vias, and more all need scrutiny in the review stage.
One example is shown in Figure 5. In order to dissipate the heat generated by the GaN devices, a large copper area and thermal vias are often used. This is a design feature generally favored by both electronic engineers and thermal engineers as large copper areas dissipate heat more efficiently, thereby achieving a higher efficiency conversion. The switching node of a half bridge connects the source node of one device and the drain node of the other. But having a large copper area effectively increases the size of the switching node, making the emission worse and hard to contain. This EMC-related risk should be highlighted in the layout design stage and a mitigation plan should be designed. In this case, a possible mitigation plan would be to use an aluminum/copper sheet over the devices. This sheet helps dissipate the heat while also providing shielding over the switching node. This contingency plan can then be implemented and tested in the packaging and mechanical stage.
Testing at an Early Stage
A preliminary test should be performed as soon as the first prototype PCB is ready. It is true that a product’s EMC performance is dependent on the layout and packaging, and the noise profile of a final product will be different from that of a single PCB. However, an early-stage, near-field probing exercise can often indicate red flags and will reap benefits at the tail end of the design process.
On the PCB level, two simple benchtop tests can be performed. Near field probing, such as using a magnetic field loop over the PCB area, can locate the noise source (see Figure 6). The noise profile is generally a good indication of both conducted and radiated emissions.6 As shown in Figure 7, measuring the common mode current on the cables using an RF current monitoring probe is another efficient way of predicting conducted and radiated emissions of the PCB under investigation.7
Packaging and Mechanical Assembly Stage
The packaging of the final product is often considered to be a mechanical job. At this stage, the final product is assembled, and the thermal design is applied. PCB assemblies could involve stacking up PCBs, stacking PCBs on stand-offs to chassis, wire-connecting PCBs, PCB connections to chassis connectors, etc. On the thermal design, for small power applications, this means applying thermal paste/glue, and thermal pads. For large power applications, this means implementing heatsinks and liquid cooling pipes.
The key challenges at this stage are to minimize connection impedance. For instance, the height of the stand-offs determines the inductance between PCBs to chassis. Therefore, multiple shorter stand-offs are preferable from the EMC point of view, a preference typically endorsed by mechanical engineers as well2. However, with stacked-up PCBs, cavity resonances could occur, and ways of de-risking resonance structures can be found in References 8 and 9.
Heatsinks need to be bonded to either 0V or power rails to prevent them from radiating emissions. Shields such as the aluminum/copper shield introduced previously also need to be bonded to the 0V plane to make them work for EMC.3 (For thermal design, they don’t need to be bonded to any point.)
Pre-Compliance EMC Testing
The two most important EMC tests for charging applications are for conducted and radiated emissions. It is always a good practice to test the products in a pre-compliance EMC test set-up before sending the unit for formal compliance testing. The good news is that both conducted and radiated emission pre-compliance tests can be performed on a benchtop at a relatively low cost.
Depending on the power rating of the DUT, suitable power rated LISNs can be used for conducted emission testing. Because it is a high voltage application, high voltage safety should take priority when setting up a pre-compliance test set-up. Using an isolation transformer and grounding the test ground plane to safety earth are absolutely necessary to secure the safe operation of conducted emission test. Figure 8 shows a benchtop pre-compliance conducted emission set-up for a product in development using GaN switches.
An open transverse electromagnetic (TEM) cell is often used to determine radiated patterns of a DUT. It should be noted that a TEM cell set-up will not deliver exactly the same quantitative results as a measurement using far-field antennas. Due to space constraints, longer wires are often wound within the TEM cell space, which also affects the radiated emission profile. Nonetheless, using a TEM cell has proved to be an effective way of predicting the radiated emissions of a DUT.
As shown in Figure 9, an OBC is placed inside the TEM cell. To draw a complete emission profile of the DUT, three main orthogonal orientations of the DUT need to be placed.10 But this also illustrates the limitations of using a TEM cell for testing large power-rated products such as on OBC due to the spectrum height of a TEM cell (in this case, this TEM cell has 15 cm spectrum height). Therefore, in this case, only one orientation of the DUT is tested. However, for home appliance charging applications, a DUT is small enough to be tested with the three main orthogonal orientations.
Hopefully, at this stage, the pre-compliance results provide a high level of confidence that the device will pass the emission tests. However, if red flags are highlighted, engineers can walk back to the previous stage to work out a troubleshooting plan that will eventually address the highlighted issues.
Sending the Product for Formal EMC Testing
There is always some degree of uncertainty when it comes to final EMC testing. But, by following the EMC management process described in this article, there should not be any big surprises. The process helps to ensure that all foreseeable EMC aspects have been considered and addressed during the design process. The meeting notes of each design review should be well-documented in an EMC risk assessment. The EMC risk assessment serves as convincing evidence that the company has at least attempted to address EMC issues.
- T. Hudson, C. Pineda, “Comparative Study of PFC Topologies: Interleaved Boost vs. Totem-Pole PFC Topologies,” MPS Application Note.
- M. Zhang, “EMC Design Techniques for Electrical Vehicle DC-DC Converters,” In Compliance Magazine, December 2021.
- K. Armstrong, “EMC Techniques for Heatsinks,” January 2021. https://www.emcstandards.co.uk/emc-techniques-for-heatsinks1
- B. Mammano, B. Carsten, “Understanding and Optimizing Electromagnetic Compatibility in Switch Mode Power Supplies.”
- B. Keogh, I. Cohen, “Flyback transformer design considerations for efficiency and EMI,” Texas Instruments Application Note.
- M. Zhang, “The Magic Loop – Techniques of using magnetic field loops.”
- M. Aschenberg, C. Grasso, “Radiation from Common Mode Currents – Beyond 1 GHz”
- M. Zhang, “Structure Resonances: Ways To Identify, Locate, and Fix EMI Issues,” Signal Integrity Journal, April 2022.
- K. Armstrong, “De-risking Resonances in Single Conductor Structures, Such as ‘Ground’,” In Compliance Magazine, October 2019.
- M. Mayerhofer, “FAQ TekboxOopen TEM-Cells,” Tekbox Application Note.