CDM Testing of Small Integrated Circuits

Integrated circuits are classified for ESD robustness using a variety of tests. The most popular tests are Human Body Model (HBM) and Charged Device Model (CDM). These two ESD classifications are intended to indicate how well a circuit will survive ESD stresses in manufacturing environments which include basic ESD controls. HBM is the oldest of the ESD tests, but factory ESD control experts generally agree that CDM is the more important test in modern, highly automated, assembly operations. The amount of stress for CDM scales with the size of the device. For that reason “conventional wisdom” on CDM has often stated that you don’t need to test very small integrated circuits because the peak currents get vanishingly small. In last month’s article for IN Compliance [1] we presented an article showing that the peak current for very small devices does not become vanishingly small as often thought. Measurements with a high speed oscilloscope demonstrated that peak currents remain surprisingly high even for very small devices although the width of the pulse gets very narrow. In the past these high peak currents were missed due to the use of 1 GHz oscilloscopes as called for in the standard for the field induced CDM test [2], the most popular form of CDM testing.


This article will discuss how testing small devices is very difficult and then present some of the ideas that have been tried to improve the testability of small devices using the field induced CDM test method.

The Problem of Testing Small Devices
The higher than expected peak currents observed for very small integrated circuits was not good news for ESD test engineers responsible for testing very small devices, with dimensions on the order of small single digit millimeters. Figure 1 shows a small 8 ball chip scale package on a field induced CDM tester. The pogo pin which must touch each of the pins being tested represents a significant fraction of the size of the entire integrated circuit. It is obvious that it would not take much of a touch to move the device being tested; requiring repeated repositioning of the device.

During field induced CDM testing it is customary to hold the device under test (DUT) in position using a vacuum. For very small devices the vacuum often does not hold the device very securely. Additionally, the vacuum hole represents a significant fraction of the size of the DUT and can affect the device stress. When the vacuum hole represents greater than about 18% of the area of the DUT the amount of stress begins to fall. Figure 2 compares the amount of stress, measured as either peak current or total charge, between devices that are over a vacuum hole and those that are not over a vacuum hole. [3]

The use of vacuum to hold devices during CDM testing therefore presents two problems. First of all it doesn’t work, and even if it did it starts to affect the test results.
Two methods have been tried in the industry to improve testability of small devices, mounting the small package on a holder of some kind or holding the device in place with a support structure or template. The two methods will be discussed below.


Figure 1: Photograph of a small chip scale packagein a CDM tester (Orion)


Figure 2: Ratios of peak current and total charge with vacuum hole (WH) and without vacuum hole (NH)


Small Devices on Holders
CDM measurements have been made on a 6µSMD under three conditions, the device only, the device mounted on a 14DIP Conversion Board and on a 36LLP Surrogate Board. These are shown to scale in Figure 3. CDM waveform measurements, Figure 4, were made on the three options at 500 V with an 8 GHz oscilloscope. The results show that mounting on a board does increase the stress applied to the integrated circuit. The increase in stress for the 36LLP Surrogate is fairly modest and might be considered a realistic tradeoff for ease of handling and more reliable test results. The increase in stress from mounting on the 14DIP Conversion board is many times more severe and probably an unacceptable compromise. The good news is that the 36LLP Surrogate was actually easier to handle than the 14DIP Conversion board which tended to move during testing.



Figure 3: 6µSMD (top left) package only; 36LLP surrogate (bottom left) with 6µSMD mounted on it; 14DIP conversion board (right) with 6µSMD mounted on it


Figure 4: Waveform comparison for chip-scale package (6µSMD) vs 36LLP (QFN) Surrogate vs 14DIP Conversion Board at 500V with 8 GHz oscilloscope


Support Template
The second method of handling small integrated circuits is to use a support template. The concern with support templates has been; how much does the presence of a dielectric change the capacitance of the integrated circuit to the field plate due to the higher dielectric constant material around the small device. The capacitance between the DUT and the field plate is the determining factor in the amount of stress on the DUT.

Figure 5 shows a 6µSMD constrained inside of a template in a CDM machine. The DUT now sits in a carefully machined hole in an insulator, which is held in place on the CDM machine’s field plate using vacuum. Figure 6 shows waveforms captured with and without an FR4 support template for a 6LLP package at 500 V using an 8 GHz oscilloscope. This shows that the template creates very little increase in the stress to the integrated circuit under test.



Figure 5: 6µSMD constrained using a support template. (RCDM3)



Figure 6: Waveform comparison with and without support template (6LLP at 500 V with 8 GHz oscilloscope


Testing very small integrated circuits for CDM using the field induced method presents significant challenges. Mounting a very small device on a circuit board can improve handling significantly but care has to be used not to make the board too large or the device will be stressed much more severely than if the device was tested without the board. The use of a template to hold the device in place during testing produces very little overstress. The manufacture of the template to hold the device securely during the testing can be a challenge. favicon


  1. R. Ashton, M. Johnson, S. Ward, “CDM Currents for Small Integrated Circuits,” IN Compliance, May 2010.
  2. “Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components,” JESD22-C101D, JEDEC Solid State Technology Association, October 2008.
  3. M. Johnson, R. Ashton, and S. Ward, “FCDM Measurements of Small Devices,” EOS/ESD Symposium Proceedings 2009.

Robert Ashton joined the Discrete Products Division of ON Semiconductor as a Senior Protection and Compliance Specialist in 2007, having previously spent 3 years in the position of Director of Technology at White Mountain Labs, a provider of ESD and latch-up testing of integrated circuits. Prior to that, Robert was a Distinguished Member of Technical Staff at Agere Systems, Bell Labs Lucent Technology, and AT&T Bell Labs, in integrated circuit technology development. Robert has published numerous articles on ESD testing of integrated circuits, test structure use in integrated circuits and CMOS technology development, and has presented tutorials on ESD, latch-up, and Transmission Line Pulse testing at IEEE and ESD Association conferences. In addition, Robert is an active member of ESDA Working Group 5 for Device Standards, ESDA Working Group 14 for System Level Test as well as the JEDEC Committee 14.1 ESD and Latch-Up Working Groups and the IEEE Surge Protection Device Committee.

Robert received his B.S. and Ph.D. in Physics from the University of Rhode Island in Kingston, RI, USA in 1971 and 1977.

Marty Johnson returned to National Semiconductor in 2006 working in ESD device design debug and supervising the ESD Characterization Lab. He currently is supervisor of the ESD Qualification & Characterization Lab. From 2001 to 2006, he worked at Philips Electronics (Semiconductor Division) focusing on WLR and TLP characterization. During his tenure at Philips he was the corporate representative to the Reliability Technology Advisory Board (RTAB, now ISMI) and its chairman in 2004. From 1978 to 2001, he worked for National Semiconductor spanning the semiconductor reliability spectrum from basic reliability qualification through wafer level reliability to ESD and Latch-up. He is also active on the JEDEC ESD Team (JC-14.1), the Joint ESDA/JEDEC HBM and CDM teams and the JEDEC Latch-up Standards team.

Marty received his B.S. Physics from Midland Lutheran College in 1973, his M.S. Physics from the University of Tennessee Space Institute in 1975 and his M.S. in Electrical Engineering from the University of Nebraska in 1978.

Scott Ward joined Texas Instruments in 2007 to work in the field of device-level ESD testing and ESD testing standards development. He has since expanded his work to include factory ESD control and handling. Prior to Texas Instruments, Scott worked for Cypress Semiconductor in San Jose, CA. At Cypress, his work included ESD and Latch-up design and characterization; as well as device testing standards development. Since 2003, he has been a member of the ESDA Working Group 5 standards committee (device testing). Scott joined the JEDEC ESD standards task force in 2005. Scott is an ESDA member, attending every EOS/ESD Symposium since his first in 1996. Scott began his career at ZiLOG in 1995, designing on-chip ESD protection networks.

Scott has an M.S. in Electrical Engineering from the University of Idaho and a B.S. in Electrical Engineering from Montana State University.