CDM Currents for Small Integrated Circuits

Integrated circuits are tested for their robustness to electrostatic discharge (ESD) using the Human Body Model (HBM) and Charged Device Model (CDM) test methods. Circuits which pass 1000 V HBM or 250 to 500 V CDM can be handled with high yield in manufacturing facilities using basic ESD control procedures. [1, 2] HBM is the oldest, best known and most widely used ESD test method, but most ESD factory control experts contend that the vast majority of ESD failures in modern manufacturing lines are better represented by the CDM test method. The CDM test method is intended to reproduce what happens when an integrated circuit becomes charged during handling, and then discharges to a grounded surface.

Field Induced CDM
The most popular CDM test method is the Field Induced CDM (FCDM) test method. [3] A schematic of the FCDM test method is shown in Figure 1. The device under test (DUT) is placed with its contact pins facing upward (in what is known as the dead bug position) on top of a field plate covered by a thin insulator. This creates a capacitance between the DUT and the field plate whose value scales with the size of the DUT. The potential of the field plate can be controlled with a high voltage power supply. As long as the capacitance between the DUT and the field plate is much larger than the capacitance between the DUT and any other part of the test system, the DUT’s potential will closely track the potential of the field plate. The FCDM test setup is completed with a ground plane that sits above the field plate. At the center of the ground plane is a spring loaded pogo pin with a 1 Ω resistor to the ground plane. The pogo pin is also connected to the center conductor of a 50 Ω coaxial cable which can be connected to a high speed oscilloscope or pulse detection circuit. Any current that flows through the pogo pin to the ground plane can therefore be sensed by the oscilloscope. The ground plane can be moved under computer control in three dimensions with respect to the field plate and the DUT, such that the pogo pin can contact any of the DUT pins.

Figure 1: Schematic diagram of a Field Induced CDM tester


A CDM test is performed as follows. An uncharged DUT is placed on the field plate, which is at ground potential. The potential of the field plate is adjusted to a high voltage, for example 500 V. Since the DUT is capacitively coupled to the field plate, the DUT potential will track the potential of the field plate. The ground plane is then moved such that the grounded pogo pin touches one of the pins of the DUT. This will ground the DUT, producing a very fast current pulse, which is sensed by the oscilloscope. This is the CDM event. The field plate is then slowly returned to ground potential with the pogo pin touching the DUT. After all elements of the test setup are returned to ground potential, the ground plane with the pogo pin can be raised and the testing can be continued with additional stresses to the same pin or to other pins on the device under test.

CDM Measurements

Figure 2 shows the measured peak current versus package area for a range of package sizes measured as specified in the JEDEC CDM standard with a 1 GHz oscilloscope.


Figure 2: Peak current as a function of package size

The data in Figure 2 makes intuitive sense. As the package size gets smaller, the capacitance of the DUT to the field plate gets smaller and therefore the peak current reduces. Since peak current is usually considered to be the best indicator of an ESD event’s ability to cause damage, there has been a question in the ESD community; at what package size does it no longer make sense to test an integrated circuit for CDM? The authors, all members of the JEDEC ESD Working Group, were asked by the committee to study CDM events on small integrated circuits, and, if possible, to recommend a package size below which CDM testing was no longer necessary.

Work by Henry et al. [4] has shown that interesting features of the CDM current pulse are masked by the 1 GHz oscilloscope bandwidth specified by the JEDEC CDM standard. A sub-team of the JEDEC ESD Task Group decided to investigate the properties of small package CDM events using an 8 GHz oscilloscope in addition to the 1 GHz oscilloscope specified by the standard. [5] Figure 3 shows peak currents versus package size measured with both a 1 GHz and an 8 GHz oscilloscope. The results do not look particularly different for the two bandwidths. The situation changes if we expand the area axis to focus on the smallest package sizes, as shown in Figure 4. At small sizes the peak current is much larger with the higher bandwidth oscilloscope. In fact, an extrapolation of the 8 GHz peak current to zero area yields a value in excess of 1 A, rather than the 0 A extrapolation predicted by the 1 GHz data.


Figure 3: Peak CDM current versus package area including both 1 GHz and 8 GHz data



Figure 4: Peak CDM currents for very small packages measured with both a 1 GHz and 8 GHz oscilloscope

This behavior can be understood if we look at the current versus time curves for a variety of sample sizes using the 8 GHz oscilloscope, as shown in Figure 5. The decrease in peak current for smaller sample sizes is evident, but it is also clear that the width of the initial peak decreases to less than half a nanosecond for the smallest samples. This exceeds the capabilities of a 1 GHz oscilloscope. The loss of signal accuracy can be readily seen if we directly compare waveforms captured with 1 GHz and 8 GHz bandwidth.


Figure 5: CDM current versus time for a variety of sample

Figure 6 shows the CDM current waveform for a 6µSMD package captured with a 1 GHz oscilloscope, an 8 GHz oscilloscope and the 8 GHz oscilloscope in 1 GHz bandwidth mode. The dramatic difference in the measured peak height for the two bandwidths is immediately apparent. The second limitation of the 1 GHz oscilloscope the sparseness of the sampling points for the 1 GHz oscilloscope with its 5 GS/s sample rate. This compares with the 20 GS/s rate used by the 8 GHz oscilloscope even in 1 GHz mode. The total charge in the current pulse is, however, the same for the three measurements.


Figure 6: Comparison of FCDM waveforms for 6µSMD (CSP) package with 8 GHz oscilloscope, 8 GHz oscilloscope in 1 GHz mode and 1 GHz oscilloscope at 500 V CDM stress

The measurements show that, for small packages, a 1 GHz oscilloscope is not adequate for characterizing CDM current pulses. The real peak current for small packages is several times larger than the value obtained from a 1 GHz measurement. It is not possible to exempt small package devices from CDM due to a vanishing peak current. It is true that the energy in the CDM pulse is extremely small due to the narrow pulse width, even though the peak current remains at an ampere or more. CDM damage is, however, not the result of silicon melting, as is the case for HBM. CDM damage is due to oxide breakdown triggered by high voltages that result from high currents during the brief CDM event. A more detailed circuit analysis would be needed before it would be possible to exempt small packages from CDM testing.

It would be easy to conclude from these measurements that the 1 GHz oscilloscope required by the JEDEC CDM test standard is inadequate. While this is a reasonable viewpoint, the use of a 1 GHz oscilloscope for daily equipment functionality verification is probably sufficient when using the JEDEC calibration modules which are large enough to not produce an extremely narrow pulse. For more detailed measurement, especially on small samples, a higher speed oscilloscope is recommended. favicon


  1. “Recommended ESD Target Levels for HBM/MM Qualification,” JEP155, JEDEC Solid State Technology Association, August 2008.
  2. “Recommended ESD-CDM Target Levels,” JEP157, JEDEC Solid State Technology Association, October 2009.
  3. “Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components,” JESD22-C101D, JEDEC Solid State Technology Association, October 2008.
  4. L.G. Henry et al, “Different CDM ESD Simulators provide different Failure Thresholds from the Same Device even though All the Simulators meet the CDM Standard Specifications,” EOS/ESD Symposium Proceedings 2006.
  5. M. Johnson, R. Ashton, and S. Ward, “FCDM Measurements of Small Devices,” EOS/ESD Symposium Proceedings 2009.

Robert Ashton joined the Discrete Products Division of ON Semiconductor as a Senior Protection and Compliance Specialist in 2007, having previously spent 3 years in the position of Director of Technology at White Mountain Labs, a provider of ESD and latch-up testing of integrated circuits. Prior to that, Robert was a Distinguished Member of Technical Staff at Agere Systems, Bell Labs Lucent Technology, and AT&T Bell Labs, in integrated circuit technology development. Robert has published numerous articles on ESD testing of integrated circuits, test structure use in integrated circuits and CMOS technology development, and has presented tutorials on ESD, latch-up, and Transmission Line Pulse testing at IEEE and ESD Association conferences. In addition, Robert is an active member of ESDA Working Group 5 for Device Standards, ESDA Working Group 14 for System Level Test as well as the JEDEC Committee 14.1 ESD and Latch-Up Working Groups and the IEEE Surge Protection Device Committee.

Robert received his B.S. and Ph.D. in Physics from the University of Rhode Island in Kinston, RI, USA in 1971 and 1977.

Marty Johnson returned to National Semiconductor in 2006 working in ESD device design debug and supervising the ESD Characterization Lab. He currently is supervisor of the ESD Qualification & Characterization Lab. From 2001 to 2006, he worked at Philips Electronics (Semiconductor Division) focusing on WLR and TLP characterization. During his tenure at Philips he was the corporate representative to the Reliability Technology Advisory Board (RTAB, now ISMI) and its chairman in 2004. From 1978 to 2001, he worked for National Semiconductor spanning the semiconductor reliability spectrum from basic reliability qualification through wafer level reliability to ESD and Latch-up.
He is also active on the JEDEC ESD Team (JC-14.1),
the Joint ESDA/JEDEC HBM and CDM teams and the JEDEC Latch-up Standards team.

Marty received his B.S. Physics from Midland Lutheran College in 1973, his M.S. Physics from the University of Tennessee Space Institute in 1975 and his M.S. in Electrical Engineering from the University of Nebraska in 1978.

Scott Ward joined Texas Instruments in 2007 to work in the field of device-level ESD testing and ESD testing standards development. He has since expanded his work to include factory ESD control and handling. Prior to Texas Instruments, Scott worked for Cypress Semiconductor in San Jose, CA. At Cypress, his work included ESD and Latch-up design and characterization; as well as device testing standards development. Since 2003, he has been a member of the ESDA Working Group 5 standards committee (device testing). Scott joined the JEDEC ESD standards task force in 2005. Scott is an ESDA member, attending every EOS/ESD Symposium since his first in 1996. Scott began his career at ZiLOG in 1995, designing on-chip ESD protection networks.

Scott has an M.S. in Electrical Engineering from the University of Idaho and a B.S. in Electrical Engineering from Montana State University.