An Overview of Transmission Lines in Electronic Systems

1711_F4_coverA Brief Guide to Identifying and Troubleshooting Signal Integrity Issues

It was not too long ago that people thought everything a microcontroller (MCU) needed would be integrated into the chip; add a power supply and some decoupling capacitors and you have a design. However, with the internet of things (IoT) revolution upon us, applications have become physically smaller and more complex, necessitating interfaces with other MCUs and external memory. These interfaces are created through the use of digital signaling occurring between systems, and until recently, engineers have designed these systems paying little attention to the physical effects of increasing edges of the clock and data signals. However, increasing the data rate puts the signal at risk of running into issues due to jitter. As a result, it is often up to that one person in the office, usually the EMC engineer, to help solve issues related to this phenomenon. Without a solid basis for understanding of how these affect performance, they too may be left confused as to why a sped-up clock suddenly results in signal integrity issues. These errors can all be attributed to the transmission line effect.

Among these most common failure modes is inter-symbol interface (ISI), resulting in a digital signal not being represented properly, as demonstrated in Figure 1.

Figure 1: Demonstrating signal loss and interference

Figure 1: Demonstrating signal loss and interference


Transmission line issues generally fall under the subheading of signal integrity, which cleverly straddles the border between hardware design/layout and traditional EMC. Using examples from both the most recent EMC symposium and SPICE, we will scratch the surface of transmission lines such that the next time a clock signal looks more like a sine wave you will feel more comfortable tackling the problem.

Where is the Transmission Line on the Schematic?

This statement most likely has frustrated many a hardware engineer when discussing why increasing the length of a data or memory bus trace has resulted in a failed checksum. We first start by examining a simple electrical circuit consisting of a voltage source (with some impedance), a medium in which the signal travels down, and the load. This system can extrapolate into any number of electrical systems:

  • Conductors on a printed circuit board (PCB), either embedded between reference planes or
    above of one; or
  • Commonly used connector cabling such as coaxial cabling, ribbon cable, or twisted wire pair.

As the signal travels down the conductor, two fields are associated with it. The first being the magnetic field associated with the current and the second being an electric field associated with the voltage. We represent these as:

  • Line inductance present in any current carrying conductor that is associated with the length of the trace; and
  • Line capacitance present in-between conductors separated by any insulating medium (often air or FR-4 material).

These two facts lead us to a basic, well-documented model of a conductor depicted in Figure 2, which is commonly referred to as the lumped parameter model.

Figure 2: Lumped Element Conductor Model

Figure 2: Lumped Element Conductor Model


However, when these conductors become physically long, their length becomes a significant fraction of the wavelength of the signal they are carrying, and the signal will undergo a noticeable phase shift between these two waves (instead of being traditionally 180 out of phase). When discussing transmission line effects, it is meant that the voltage and current in the propagating wave will be at minimum and maximums at different points along the conductor. To model this, we can ‘cut’ the conductor into pieces and model each piece with an inductance and capacitance characteristic of that medium. In addition, you will have to take into account the losses attributed to the skin effect and dielectric loss as series and parallel resistors. This is done in Figure 3.

Figure 3: Distributed element conductor model

Figure 3: Distributed element conductor model


Thus, we can define a transmission line by its electrical length in comparison to its physical length. A common rule of thumb is that a conductor should be treated as a transmission line if its length is greater than 1/10 of the wavelength of the signal traveling on it as demonstrated in (1):

1711_Semanson_eq1    (1)

It is important to remember that in the case of looking at the wavelength of the signal, you are concerned not just with the fundamental frequency of the signal on it but also by any harmonics of the intended (or unintended) signal. In the time domain, we look to the rise time of the digital signal, compare that to the propagation delay, and trace length of
the conductor; we then look for it to fulfill the following criteria:

1711_Semanson_eq2     (2)

When the conductor fulfills either of these criteria, characteristics we expect about a traditional conductor, become less ideal. Examples are:

  • As soon as the signal is transmitted, it will be received. On the contrary, the delay it takes for the signal to travel from the transmitter to receiver is finite and measurable.
  • Expecting the line to be an ideal conductor, and as such, there will be no signal loss as the signal arrives at the load. In fact, there will be parasitics that react, resulting in attenuation or ringing due to impedance mismatching.
  • The signal traveling on the conductor is free of any reflections/interference on the conductor such that the square wave is accurately represented at the receiving end of the conductor. Any time the signal encounters a change in impedance either at an interconnection point such as a via, or at the load, we could get reflections or echoes back on the conductor causing interference.

Now that a mental model of a transmission line has been created, think about a signal injected onto the conductor and what the wave “sees” as it propagates down the line. Because it takes a finite time to propagate to the load, the signal does not immediately “see” the load. This allows us to relate the voltage and current produced by this traveling wave by the characteristic impedance shown in (3). To start, we will ignore additional parameters such as ohmic and dielectric losses.

1711_Semanson_eq3    (3)

It is important to note that this characteristic impedance is not something that is measurable by a voltmeter (you can try, but you will get the resistance of the conductor), but is created by the incident electromagnetic wave (or more simply put, the rising edge our aforementioned digital pulse) traveling down the medium. And, since the conductor simply guides the energy as it propagates through the dielectric medium, we can characterize the speed of the wave as shown in (4).

1711_Semanson_eq4    (4)

Since the velocity of propagation is a function of the material that is also linked to the line inductance and capacitance, we can use that relationship to come up with the following, relating the velocity of propagation to the inductance and capacitance (5, 6).

1711_Semanson_eq5    (5,6)


Therefore, transmission lines can be characterized by the following:

  • The characteristic impedance of the line, in situations such as coaxial cables, it’s known. In others such as PCB traces we have to rely on either a tool or hand calculations.
  • The velocity of wave propagation, which requires us to know the type of dielectric. This is often the PCB material or insulation of a coaxial cable.
  • The length of the line, as that determines the propagation delay of the signal. We can use this relationship to determine the propagation delay as a function of length and speed of the signal. Below you will find the delay for a coaxial cable (7).

1711_Semanson_eq7     (7)

Now that we have the idea that transmission lines are not a specific component we place in a schematic but a useful construct created to help characterize and examine signal integrity problems, we can use SPICE to examine a common effect that happens at impedance mismatches.

Impedance Discontinuities

Taking our example from earlier and expanding upon the basic building blocks of a transmission line along with our newfound knowledge that the conductor has a characteristic impedance and some finite delay, we can use SPICE to characterize one of the most prominent transmission line effects – reflections.

Reflections occur any time power is not transferred through an interconnect or load perfectly which occurs when the interconnect does not have the same impedance as the characteristic impedance of the cable. For this reason, you see many papers modeling the impedance characteristics of a via, as well as micro strip lines. In order to examine these reflections, we define two terms: The load and source reflection coefficient, ρsource and ρload.

We start with the diagram in Figure 4.

Figure 4: Basic transmission line setup

Figure 4: Basic transmission line setup


As the current is delivered to the load, the load current becomes the incident current subtracted from the reflected current, while the load voltage is the incident voltage added to the reflected voltage. This relationship is stated as follows:

1711_Semanson_eq8     (8,9)


Next, using (8,9) we need to relate the incident voltage to the reflected voltage. By doing this, we can create a ratio where we can define a reflection coefficient. To do this, we note that the load current is the difference of the reflected and incident voltages over the characteristic impedance of the cable.

1711_Semanson_eq10      (10)

Combining (8), (9), (10) and ohm’s law, the result is the following relationship (11).

1711_Semanson_eq11     (11)

Thus, using a little bit of algebra, we can define a voltage ratio at the load (12).

1711_Semanson_eq12     (12)

From this, we can define the two reflection coefficients we discussed earlier as,

1711_Semanson_eq13      (13,14)  


In addition, from this we can draw three distinct conclusions regarding the load voltage’s effect on the reflected voltage:

  • If the load impedance matches that of the transmission line, then the incident power is absorbed and there will be no reflection;
  • If the load impedance is below that of the characteristic impedance of the transmission line, then we see a negative reflection; and
  • If the load impedance is above that of the characteristic impedance of the transmission line, then we see a positive reflection.

While this is an interesting phenomenon, these reflections will cause constructive/destructive interference with meaningful information resulting in errors. Sometimes these reflections will be depicted in something called a lattice diagram. These diagrams demonstrate the reflected voltages at each interconnect as a function of the reflection coefficient described in (13, 14). An example lattice diagram is shown in Figure 5.

Figure 5: Lattice diagram transmission line setup

Figure 5: Lattice diagram transmission line setup


To demonstrate these scenarios, we can use SPICE and the included transmission line model to show how these pulse signals can interfere with each other. The simulation will be setup as shown in Figure 6.

Figure 6: SPICE circuit for simulation

Figure 6: SPICE circuit for simulation


In Figures 7, 8 and 9, we see three different diagrams matched to their three different situations as previously described.

Figure 7: Simulation result for match load/source/transmission line

Figure 7: Simulation result for match load/source/transmission line


Figure 8: Simulation result for unmatched load (shorted load) to transmission line

Figure 8: Simulation result for unmatched load (shorted load) to transmission line


Figure 9: Simulation result for unmatched load (open load) to transmission line

Figure 9: Simulation result for unmatched load (open load) to transmission line


Material Dissipation factor
Vacuum/Free Space 0
Polyethylene 0.0002
Teflon 0.0002
Ceramic 0.0004
Polypropylene 0.0005
FR4 Epoxy Glass 0.02
Figure 10: Table outlining different dissipation factors gives you an idea of losses associated with dielectric

In controlled situations like these, it may seem as if reflections are not something that is concerning for signal integrity purposes, but for continuous transmissions, it is of major concern each time a discontinuity exists. Multiple reflections reflected back into the transmission line could arrive at the transmitter with almost any amplitude depending upon how complex the situation is, and at any phase angle. After demonstrating how a signal travels down a transmission line and what happens when encountering an impedance discontinuity, we now turn our attention to losses in the line as we attempt to better characterize a transmission line.


The more we look into conductors carrying digital signals with quick rates of change, the more we realize that they are not as passive as we first thought. With reflections being problematic at impedance discontinuities, we encounter another type of non-ideal characteristic that is exacerbated at high frequencies:

  • Conductor loss due to the resistance of the conductors; and
  • Dielectric loss resulting from the dielectric material absorbing energy from the propagating energy.

While characteristic impedances are a function of the dielectric used in the transmission line, as well as the line geometry itself; ohmic losses are characteristics of the conductor itself. This type of loss comes in two varieties: The skin effect (which is dependent upon the conductor shape), and the DC resistance of the conductor. It is important to note that this discussion is for two conductors we are treating as a transmission line that are of similar dimensions and shapes. In the case of coax or a stripline/microstrip trace, then most of the resistance will result from the smaller conductor carrying the signal. In this situation, it is often practical to neglect the losses from the resistance of the larger conductor, which is often the return.

However, dielectric loss is dependent upon the insulating/dielectric material separating the two conductors making up the transmission line. We define this loss by its ability to dissipate energy in the material. This dissipation factor is defined as the ratio of the energy stored to the energy dissipated in the material, per hertz (you will find this in books as the tangent of the loss angle, tan(δ)).

While there are books dedicated to investigating dielectric loss, the dielectric material is often fixed while the frequency is not. Thus, the important item to note when it comes to discussing transmission line losses is that the loss due to the physical medium of the conductor varies in proportion to the square root of frequency, while the dielectric loss varies linearly. An equation relating the two loss types together is found in (15).

1711_Semanson_eq15    (15)

The key takeaway from (15) is the relationship that the dielectric conductivity (G) and resistive losses (R) form, and if very high frequencies or data rates (above a GHz) exist in your application, dielectric material is going to be of concern.

While these last two sections are not meant to be exhaustive regarding non-ideal characteristics of transmission lines, they are meant to get the reader into the correct mindset when discussing high-frequency signals on their conductors. Next, we’ll discuss the how and why, when it comes to terminations.

Transmission Line Termination

After learning about losses and reflections, we now have some idea that impedance mismatch with the transmission line’s characteristic impedance is less than ideal. Now we can look at an example shown in Figure 11, where on the left we see what we expect through a properly terminated or matched digital signal, and on the right what some readers have probably gotten – an improperly terminated signal. This is a result of undesired effects of unmatched traces and loads, and there are different methods available to correct this.

Figure 11: Digital signal that we want (left), digital signal that we get (right)

Figure 11: Digital signal that we want (left), digital signal that we get (right)


While no standard termination works because of the complexities of layouts, cost, power considerations, and allowed components, there are in general four types of terminations utilized today:

  • Series termination with a resistor, or sometimes called a source termination, places a resistor close to the source or transmitter of the digital signal;
  • Parallel termination with a resistor, or sometimes a thevenin network termination, if two parallel connections are used;
  • Device termination with a diode, or RC network;


  • No termination at all. Here, the designer must control the length and geometry to regulate the impedance of the critical trace being treated as a transmission line (usually this results in a maximum line length being set in the design tool).

Each of these methods deals with the perceived ringing or overshooting in different ways. The values, motivation (such as cost, or operating condition), and placement of these components in your system is involved and the goal of this article is to start to give you an idea of “why” when you look to a reference design or application note and see one of these methods used.

Series Termination

The sign of a series termination is when you see a resistor placed on the output of the transmitter (usually a logic gate) and the transmission line.


Figure 12: Example of series termination

Figure 12: Example of series termination


We choose the resistance by estimating the characteristic impedance of the transmission line, and subtracting that from the output impedance of the logic gate shown in (16).

1711_Semanson_eq16      (16)

By doing this, we will see ringing because the input impedance of the gate is much greater than the impedance of the line, and as a result, a reflection will propagate back to the source. In this case, it is met with the series termination resistor, and will dampen the reflection. The reflection is damped because the combined impedance of the series resistor and the driver has output impedance comes close to matching the characteristic ( of the transmission line).

This type of termination is best when:

  • The load is lumped at the end of the trace.
  • When the driving devices impedance is less than the characteristic impedance of the trace.

The concern for this type of connection is for violating driving voltage limits (either or ), and thus is advised only for point-to-point loads. In addition, matching the output impedance of the circuit driver could prove difficult when it comes to manufacturability due to variability in the line driver manufacturing process.

Parallel Termination

Parallel types of terminations are among the most prevalent types of terminations used in embedded systems and is most commonly seen in in distributed communications busses.

Figure 13: Example of parallel termination

Figure 13: Example of parallel termination


They are identified by a parallel termination across the differential lines (signal to ground) at the far end and are used to eliminate reflections on that line. The resistor value here is selected to be slightly higher than the characteristic impedance of the transmission line in which it is terminating. Care must be taken when comparing the data rates to the termination resistance. Too high of a resistance will result in a low pass filter being formed with the parasitic trace capacitance, which will result in slowing the rise/fall of the signal. And consequently too small of a resistor could result in loading down the bus, resulting in unwanted power consumption. We must make sure that the driver circuit can handle this increase.

Often you may see another resistor placed from signal to power as well (sometimes called a thevenin network). If done, the parallel combination of these resistances must equal the characteristic impedance of the line. Many will recognize this as a pull-up, pull-down scheme used in TTL schemes.

Device Termination

Device termination is a broad classification we use for a resistor-capacitor (RC, or AC termination), or diode type of termination.

Figure 14: Example of AC or RC termination

Figure 14: Example of AC or RC termination


The resistor in this combination matches the impedance of the line, while the capacitor works as local storage of energy holding the DC signal component and allowing AC current to flow. The resistor is picked to match the characteristic impedance of the transmission line, while the capacitor is picked to match the round-trip delay of the cabled divided by its characteristic impedance (17) in order not to slow the signal’s rise or fall.

1711_Semanson_eq17-2     (17)

Diodes on the other hand have very low power dissipation and simply clip the ringing to approximately the breakdown voltage of the diode. Attention must also be paid to the switching frequency in relation to the response time of the diode.

Figure 15: Example of diode termination

Figure 15: Example of diode termination

While used as a way for terminating differential networks, it is important to remember that unlike the previously discussed methods, in this situation, no power is dissipated and as such no reflected energy is absorbed. This could result in reflections.

Examples of a Transmission Line and SI Analysis

Now that we have discussed what is considered a transmission line, some of their unique characteristics, and how to terminate them, we will shift the discussion towards the more practical aspects of transmission lines namely:

  • Where can we expect to find these in electronic systems?
  • How can we measure improvements?

As we stated in the first section of this article, any transmitting medium can be considered a transmission line but does not show transmission line effects until the distance or the speed of the digital signal starts to become an issue. However, some very common types of transmission lines that occur in electronic systems are the:

  • Microstrip trace, where the copper trace is either running on the surface or embedded inside the PCB bordered by a single reference plane, separated by a dielectric (usually the PCB material);
  • Stripline trace, where the copper tracer is running sandwiched between two reference planes separated by a dielectric (usually the PCB material); and
  • Coaxial or ribbon cabling, in which the signal line is separated from the shield by an insulator or in the ribbon cable’s case, air.

Luckily in the case of coaxial cabling, the characteristic impedance of the cable is well documented and usually controlled by the manufacturer. However with traces on a PCB, you as the designer are usually at the mercy of napkin calculations, or whatever tools you can find through your design software. To prove the characteristic impedance and unloaded propagation delay would be the subject of an academic text book, so instead they’re included in the pictures below and can be used as a first order way of estimating and . In these estimations, we assume an unloaded line, and normal PCB material.

Figure 16: Unloaded microstrip characteristic impedance and delay

Figure 16: Unloaded microstrip characteristic impedance and delay


Figure 17: Unloaded stripline characteristic impedance and delay

Figure 17: Unloaded stripline characteristic impedance and delay


To measure how reflections, mismatched impedances, and crosstalk cause jitter or glitches on data being sent over the transmission line, engineers rely on something called an eyediagram. In addition to analyzing a multiport interconnect or network in order to determine which frequencies may result in a problem, they rely upon scattering parameters from a network analyzer.

An eye diagram measures the deviation of the rising and falling edge of a repeating digital signal and overlays them on each other. An example of this is shown in Figure 18.

Figure 18: The creation of an eye-diagram from bit sequences (011, 100, 001, and 110).

Figure 18: The creation of an eye-diagram from bit sequences (011, 100, 001, and 110).


It contains a large amount of information about a digital signal and makes the measurement of that signal irrespective of how infrequently the transitions occur.

Figure 19: The eye diagram explained

Figure 19: The eye diagram explained


Moreover, as such, in a perfect eye diagram, we would expect these diagrams to look like perfect rectangular boxes. However, jitter occurs when the rising and falling edges occur at different times, rather than their ideal clock determined time. This could be because of an impedance mismatch, crosstalk, or even process-related variations in the silicone, which results in a visible jittering of the signal.

In addition, while eye diagrams look at the digital signal, we use scattering parameters produced by network analyzers as tools to determine the quality of an interconnect. In Figure 20, we measure the reflections at each of the ports with respect to another port. This diagram is for a two-port analysis.

Figure 20: Network analyzer parameters

Figure 20: Network analyzer parameters


The s-parameters describe the behavior of the network in which it is connected, in our case the transmission line, under the stimulus of various electrical signals. The traditional signal path is from the source to the load and back, which is described by coefficients S21 and S12, while the reflections at each port are described as S11 and S22. The result is a phase and amplitude response, producing a transfer function-like response of the system tested.


Transmission lines are nuanced constructs and the answer to what seems like a relatively simple question of ‘When is my conductor, interconnect, or system a transmission line,’ does not have an easy answer. In summation, these systems are always transmission lines because they handle a propagating wave front, but the effects discussed, such as reflections, and time delays as well as losses don’t come into effect until long runs or high frequencies (or, if you are really unlucky, both). By understanding the characteristic impedance of the medium as well as the losses, we gain a good idea as to how the signal attenuates. By learning how to terminate the system properly and then measure the before and after effects on your system, you stand a much better chance of answering that tough to answer question of why checksums are not matching. 

author semanson-chrisChristopher Semanson works at Renesas Electronics America Inc. as an Electrical Applications Engineer in Durham, NC supporting a wide variety of general purpose applications. He has five years previous experience in EMC Education at the University Of Michigan, teaching EMC and Electronics with Mark Steffka. He has a bachelor’s degree in Electrical and Computer Engineering and a master’s degree in Electrical Engineering from the University of Michigan Dearborn. Chris can be reached at


About The Author

Chris Semanson

Christopher Semanson works at Renesas Electronics America Inc. as a Staff Power Systems Applications Engineer in Durham, NC supporting the design of PMICs and other power generation semiconductors in automotive applications in accordance with ISO 26262. He has five years previous experience in EMC Education at the University of Michigan, teaching EMC and Electronics with Mark Steffka. Semanson has a bachelor’s degree in Electrical and Computer Engineering and a master’s degree in Electrical Engineering from the University of Michigan Dearborn. He can be reached at

Related Posts

2 Responses

  1. Joshua Lansford

    Hello, you got a typo in the equation for the load voltage. You have it set as the sum of the incident and reflected currents instead of incident and reflected voltages.
    Also I don’t follow going into equation (10) as I would think the substitution is from
    I_load = V_load / Z_o but if V_load = V_inc – V_ref, I am not sure why in equation 10 the voltages are added instead of subtracted.

    • Joshua Lansford

      In my comment about the typo I forgot to say I appreciated the article. It is nice to have a zoomed out overview of a topic to get a complete picture which doesn’t involve too much detailed information.


Leave a Reply

Your email address will not be published.