Advances in CMOS Technologies Leading to Lower CDM Target Levels

Can you continue aiming for typical CDM protection levels?


The ESD Design Window (ESD-DW) has been steadily shrinking over time due to technology scaling not only from a smaller feature size but also as the device’s architecture has changed over time. Higher speed interfaces are driving the need for lower capacitive loading and higher on-resistance ESD devices. As package sizes increase, peak CDM currents increase as well, putting additional pressure on making improved ESD devices in each new technology generation. As technologies scale, metal resistance at lower metal levels continues to increase, which contributes to increasing the clamping voltages within ESD devices. 

The above factors contribute to significant challenges in meeting the generally accepted CDM targets of 250V or 500V. Meeting functional performance and CDM existing targets can be nearly impossible for some types of I/O interfaces depending upon the type of circuit topology used in each design. In this article, we will describe the ESD-DW and the reasons for its continued shrinking. These effects mentioned are summarized in Figure 1 are driving the need for lower CDM targets.

Figure 1: Factors driving the need for lower CDM ESD targets

Goal of an ESD Protection Network

The key goal of the ESD protection device/network on any semiconductor integrated circuit (IC) product is to ensure if an ESD event does occur to any pin of the IC, that pin does not get damaged. It is necessary that any robust ESD protection device added to the pin can handle and divert the ESD event current away from the sensitive internal circuits of the IC. A basic ESD protection network using ESD elements (such as diodes) and Power clamp is shown in Figure 2. 

Figure 2: Basic circuit topology of an ESD protection network

In addition, the overall ESD protection methodology needs to ensure that during an ESD discharge, the protected internal circuit devices should not breakdown due to the increased voltage drops across the parallel ESD devices. 

The ESD-DW is defined as the region between the IC operating voltage (Vop) and the circuit breakdown voltage (Vbd). The ESD-DW shown in Figure 3 defines a visual representation of the voltage and current range, where the ESD protection devices need to operate to protect the I/O and supply interfaces. 

Figure 3: ESD-DW Visual Representation

ESD protection devices should not turn on during the normal IC functioning voltage range (IC Operating Area), nor should they operate in the IC Reliability Constraints region beyond the internal circuit breakdown voltage (Vbd) during an ESD event. The ESD-DW (Vbd – Vop) has shrunk significantly as technologies scale due to the reduction of the output device trigger voltages and receiver device oxide breakdown voltages [1]. This is quantitatively highlighted in Figure 4, which shows how the ESD-DW has scaled, going from 350nm down to 12nm technology nodes. The design window has shrunk by approximately 65% scaling from 350nm down to 12nm. 

Figure 4: ESD-DW versus Technology Node.

What are the new technology advances driving the lowering of ESD CDM targets?

Technology scaling has resulted in the IC operating voltage slowly reducing and flattening out in the 0.5 to 1.2 volt range [2]. It has also resulted in a reduction of MOSFET drain/source breakdown (bipolar turn-on) and oxide breakdown voltage under ESD conditions. Specifically, the reduction of the driver device trigger voltages are driven by a decrease in effective gate length, while the reduction in receiver device oxide breakdown voltages are driven by the decreasing gate oxide thickness. These trends are shown for the thin-oxide NFET devices in Figures 5 and 6. 

Figure 5: Thin-oxide (SG) NFET trigger voltage Vt1 vs. Technology Node


Figure 6: Thin oxide (SG) NFET Oxide Failure Voltage (Vgox) vs.
Technology Node

The decreasing metal interconnect thickness due to technology scaling has also resulted in increased lower metal level resistances, such as shown in Figure 7 for first level metal leading to higher potential wiring resistances within ESD devices, especially in the design of low capacitance ESD devices with a limited number of metal levels used to reduce back end of line capacitance in these devices. Figure 7 shows the Metal 1 sheet resistance ratio trend in multiple technologies relative to its value in a 180nm technology. For example, the Metal 1 resistance in 45nm is about 18X the value in 180nm. The temperature increase with this resistance increase, and reduced power handling of the device also leads to the thermal (y-axis) shrinking of the ESD-DW.

Figure 7: Metal 1 resistance ratio relative to 180nm vs. Technology Node

What are the trends in package sizes?

The increasing trend for more computing power has led to increasing package pin count and overall package size. Figure 8 shows this trend. Increasing package sizes lead to higher CDM peak current, as shown in Figure 9. These trends are leading to further challenges to achieving CDM ESD targets [3], [4]. 

Figure 8: Package pin count vs. year


Figure 9: Peak Current vs. Package Size

What are the trends in high-speed interface data rates?

Figure 10 shows the trend of increasing High‑Speed Serial (HSS) link data rates with technology scaling. Increasing data rates requires a reduction in the ESD device capacitance, typically resulting in smaller ESD device areas. This is in contrast to the previously mentioned need for larger ESD devices to handle larger CDM current when package sizes increase.

Figure 10: HSS maximum data rates vs. Technology Node

What are the next steps in CDM target reductions?

The impact of the ESD-DW reduction applies to any type of I/O ESD protection strategy but is most critical for ICs that have ultra-high-speed interfaces in advanced technologies, which are often packaged in larger packages. These high-speed interfaces most always use thin-oxide devices, where the need for high-speed performance does not allow for the addition of secondary ESD protection devices. In fact, high-speed interfaces have the additional challenge of requiring reduced ESD device capacitance. Larger package size ICs lead to larger CDM currents for a given CDM voltage (up to 2A to 2.5A per 100 volts of CDM voltage). In addition to larger CDM currents, in advanced technologies like 7nm, the Vt1 trigger voltage of thin-oxide driver devices is as low as 3.2V. Given the driving factors discussed as technologies scale (smaller ESD-DW, lower capacitance budget for ESD, higher metal Rs at lower metal levels, larger package sizes leading to higher peak currents), a realistic target coming on the horizon is in the 125-150 volt range for CDM target levels for high-speed/RF interfaces in advanced technologies. This reduced CDM target is currently under development and will be presented in more detail in the upcoming revision of the ESD Industry Council White Paper 2 on CDM [4]. 


  1. J. Di Sarro, K. Chatty, R. Gauthier, E. Rosenbaum, “Study of Design Factors Affecting Turn-on Time of Silicon Controlled Rectifiers (SCRS) in 90 and 65nm Bulk CMOS Technologies,” in Proc. International Reliability Physics Symposium, pp. 163-168, 2006
  2. R.Gauthier “Technology and ESD Challenges Towards 7nm,” Tutorial EOS/ESD Symposium 2018, pp. 46-67
  3. A. Jahanzeb, Y-Y. Lin, S. Marum, J. Schichl, C. Duvvury, “CDM Peak Current Variations and Impact Upon CDM Performance Thresholds,” Proc. EOS/ESD Symposium 2007, pp. 283-288
  4. White Paper 2 update: A Case for Lowering Component Level CDM ESD Specifications and Requirements, Industry Council on ESD Target Levels – to be published 2021

Founded in 1982, EOS/ESD Association, Inc. is a not for profit, professional organization, dedicated to education and furthering the technology Electrostatic Discharge (ESD) control and prevention. EOS/ESD Association, Inc. sponsors educational programs, develops ESD control and measurement standards, holds  international technical symposiums, workshops, tutorials, and foster the exchange of technical information among its members and others.

Mujahid Muhammad is an ESD Design Engineer at GLOBALFOUNDRIES with more than 20 years of experience in the field of ESD and Latchup. He presently leads a group of industry wide ESD experts on updating the Industry Council White Paper 2 on CDM Targets and eventually the JEDEC JEP157 standard. 

Robert Gauthier has led the worldwide ESD/latchup team within GlobalFoundries. He is currently on the ESDA Board of Directors and an active member on the ESDA EXCOM team. He was one of the founders of the International ESD Workshop (IEW) and is a former General Chair of the EOS/ESD Symposium.

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