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Are Your ESD Tote Boxes and Containers Too Conductive?

Current, not voltage, causes ESD damage to electronic devices, circuit boards and assemblies

Common items used in electrostatic discharge (ESD) protected work areas (EPA) are plastic totes, trays and boxes. In most cases, these are viewed as commodity items with very little thought or engineering put into their acquisition and implementation. However, they can be critical because they are used to protect the devices, circuit cards, and assemblies that are transported within them. Certainly, they must protect the part mechanically, but they must also protect the assemblies electrically. 

However, just what does electrical protection include? It is important to understand that current, not voltage, causes ESD damage to electronic devices, circuit boards and assemblies. Selection of handling and packaging materials that may come in contact with electronics must be both static dissipate and homogeneous to adequately limit discharge currents to prevent charged device model (CDM) or charged board events (CBE) related ESD damage. Most users realize that these items must not carry a charge that would result in an electrical field that can induce a voltage into the sensitive electronics that are in close proximity or enclosed within them. To accomplish this, tote boxes and trays are frequently manufactured from static dissipative or conductive materials so that any generated charge on the material is bled to ground when the transportation item is grounded. 

In many situations, users believe that “the more conductive the better;” however with the proliferation of devices that are more and more sensitive to CDM damage and CBE, placing devices and assemblies into a conductive container may produce damaging discharge currents. Experience in countless factories has indicated that over 50 percent of black ESD materials have less than 105 ohms surface resistance measurement (SRM) and, thus, are too conductive for CDM and CBE protection. Further, SRM can be misleading. Tests and manufacturing results discussed below have proven that some static dissipative materials can still produce significant and possibly damaging discharge currents. 

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Background on CDM, CBE, Class 0

Charged-Device Model (CDM)

Human-body model (HBM) has been the main thrust of ESD control and protection for the last two decades. During that time, HBM ESD failures have become rare. Parallel to this, ESD failures related to device charging and production equipment have increased. In fact, many companies now report that CDM is the cause of greater than 99 percent of ESD failures. The CDM, which best represents these failures, produces very different stress than the HBM and thus requires different device tests and factory controls. However, the development of CDM tests has been slow because of the relatively high-speed nature of the CDM-current pulse compared to HBM. And the implementation of CDM controls has been slow because of the variety of ways the CDM stress can be realized in actual production. 

Because of this, only a few companies initially pursued CDM controls and requirements1 and it is only in the last few years that the issue has become so severe that the IC industry has produced a series of white papers2 describing the emerging relative importance of CDM and HBM. 

1R. Renninger, M-C. Jon, D.L. Lin, T. Diep and T.L. Welsher, “A Field-Induced Charged-Device Model Simulator”, EOS/ESD Symposium, pp. 59-71, 1989.

2Industry Council on ESD Target Levels. A) White Paper 1: A Case for Lowering Component Level HBM/MM ESD Specifications and Requirements,” August 2007, at www.esda.org; B) “White Paper 2: A Case for Lowering Component Level CDM ESD Specifications and Requirements,” Revision 2, April 2010, at www.esda.org.

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The following excerpt is from White Paper II: 

“CDM has become the primary real world ESD event metric describing ESD charging and rapid discharge events in automated handling, manufacturing and assembly of IC devices. Its importance has dramatically increased in the last few years as package feature sizes, capacitance and pin count have scaled upward.” 

The following roadmap from this paper summarizes the situation.

Charged-Board Events (CBE)

Most IC failure analysis (FA) data, which is based on knowledge of failure signatures seen in standard HBM and CDM tests, has caused many to conclude that ESD failures are relatively rare when compared to other electrical failures commonly classified as electrical overstress (EOS). Recent data and experience reported by several companies and laboratories now suggest that many failures previously classified as EOS may instead be the result of ESD failures due to CBE.[1] A charged board stores much more energy than a device (IC) because its capacitance is many times larger. In fact, the charge (energy) transferred in the event is so large that it can cause EOS-like failures to the components on the board. 

Many FA experts identified the failure in Figure 2 as EOS even though it was actually a CBE-induced failure. Unfortunately, many failures are misdiagnosed as EOS because FA engineers are not aware of CBE. This distorts the common Pareto chart for IC defects (Figure 3). The actual occurrence of ESD is therefore likely to be significantly higher than is often reported.[2]

 

Figure 1: Combined projected effects of technology node, IO design, and IC package size on CDM thresholds
Figure 1: Combined projected effects of technology node, IO design, and IC package size on CDM thresholds

 

Figure 2: CBE ESD damage
Figure 2: CBE ESD damage

 

Figure 3: Typical IC device defect analysis
Figure 3: Typical IC device defect analysis

Class 0

Class 0 is a shorthand term for devices with an HBM or CDM threshold less than 250 volts. The ESD Association has established a subcategory at 125 volts for both HBM and CDM. Experience has shown the need for an additional subcategory at 50 volts. Class 0 device sensitivities require special handling considerations and these special handling procedures escalate with each lower subcategory. 

Preventing CDM and CBE Damage

Damage to integrated circuits, magneto-resistive heads and other sensitive electronics occurs when an extremely fast discharge current occurs upon contact between circuitry and another conductive item. This “rebalancing” of charge, when it occurs in an uncontrolled fashion, results in CDM damage and is often misdiagnosed as EOS at the circuit board level. It is important to understand that current, not voltage, is the determining factor in these events. The rebalancing of charge can be done in a controlled way, preventing a damaging CDM/CBE event. 

Two primary methods have been employed in the industry to reduce CDM and CBE damage. Both will minimize discharge currents and, thereby, ESD damage. Method one involves lowering electrostatic potentials on ESD sensitive electronics by managing static generating materials and/or neutralization of charge via ionization (See Figure 4). This method is commonly included in industry standards, whereas, method two is not. However, ionization takes a finite amount of time and complete removal of charge may not be possible for a variety of reasons. This method is especially problematic for Class 0 ESD sensitivities and charged boards. 

Figure 4: Schematic of methods used to control CDM and CBE discharges
Figure 4: Schematic of methods used to control CDM and CBE discharges

 

Method two involves managing material properties and SRM at the point of contact with ESD-safe electronics to reduce peak discharge currents. This method is highly effective for Class 0 and charged boards. It is often more cost effective, more robust and less prone to human error than method one. However, the material must be homogenous as well as static dissipative to avoid the high discharge currents discussed below. The optimal surface range is 106 to 109 ohms. It is important to note that a discrete resistor does not provide protection from these fast transients. Additionally, re-balancing of the charge by making contact between the ESD-safe device and a conductive item can actually induce damage during the connection. 

This phenomenon can be partially explained by understanding that the CDM damage occurs with high peak currents and pico-second rise times. Therefore, this is a high frequency event that does not follow Ohms law and, as a result, often leads to improper assumptions such as the discrete resistor example above. It is important to understand higher homogenous surface resistance at the right location in the discharge path can reduce discharge currents to safe levels. 

The efficacy of method two is well documented by Bell Labs Research, numerous magneto-resistive (MR) tape head papers at the EOS/ESD Symposium and manufacturing yield improvements for Class 0 devices. Figure 5 illustrates this assertion with dramatic manufacturing yield improvements that were the result of advanced CDM training and then strategic implementation of dissipative materials and tools. (For more information, go to http://www.dangelmayer.com/
class-0-case-studies.php

Figure 5: Yield improvements due to strategic use of static dissipative materials
Figure 5: Yield improvements due to strategic use of static dissipative materials

 

Many carbon-loaded ESD handling materials (around 50 percent) such as tote boxes, parts bins and packaging materials are too conductive for prevention of CDM and CBE damage. A survey of commercially available totes and bins revealed that most are too conductive, and some that are static dissipative still produce high discharge currents (see Table 1).

Surface Resistance Range

Peak Current @ 500 Volts (if tested)

ESD Events Detected?

Ceramic Material

107 to 108 ohms

0.6 to 5.1 mA

No

Dissipative Polymer

106 to 108 ohms

124 to 508 mA

Yes

Tote Material A

105 to 106 ohms

0.03 to 1.2 mA

No

Tote Material B

102 to 104 ohms

100 to 132 mA

Yes

Tote Material C

1010 to 1012

Not tested

Exceeds Dissipative Range

Not Tested

Tote Material D

102 to 103

Not tested

Not Static Dissipative

Yes

Tote Material E

102 to 103

Not tested

Not Static Dissipative

Yes

Tool Material F

108 to 109

256 mA (@500V)

Yes

Table 1: Resistance and discharge behavior of tote box/bin material

Discharge Current Issues in Packaging/Handling Materials

Because of these concerns, testing of different static dissipative tote box materials was undertaken to determine if the materials that have surface and volume resistance values generally used in the industry for ESD-safe packaging would limit discharge currents when a charged item was placed in a package or if the package was charged and placed on a conductive material.

One sample tote “Material A” made of injection molded dissipative polymeric and a sample tote made from “Material B” were subjected to testing to determine the peak current that is transferred to a grounded conductive probe when the polymeric item was charged to various voltages. This data was compared to previous data collected on metal tools, a dissipative ceramic material, and a static dissipative polymeric material (Figure 6) that utilized carbon fiber as the conductive element. In addition, surface and volume resistance values of the two subject materials (along with other commercially available totes and bins) were measured and are reported in Table 1.

Figure 6: Dissipative polymer - discharge current waveform
Figure 6: Dissipative polymer – discharge current waveform

 

The Material A sample exhibited discharge currents in the same range as state-of-the-art dissipative ceramic materials, orders of magnitude lower than metal, Material B, and other “dissipative” polymeric materials. Further no ESD events were detected during the grounding of the Material A polymer. Material B samples exhibited high discharge currents, with visible sparking. ESD events were detected with this material with applied voltages of 200 volts.

Experimental Procedure and Discussion

A test setup similar to that seen in Figure 7 was used to test the samples. A 5” x 4” flat section was cut out of the tote manufactured from Material A and used for testing. Material B was supplied as a 5” x 5” sample plaque. The samples were held in an insulative clamp and then charged to various voltages. A CT-1 current probe was used to measure the current that passed through a wire that was connected to ground as it made contact with the charged sample. The peak currents measured by the current probe were measured with approximately 50 discharges at each voltage level to provide enough data for statistical sampling. While the discharge currents were measured, an ESD event detector was used to determine if EMI from an ESD event occurred during the discharging step. The detector sensitivity was set to detect events as low as 10 volts.

Figure 7: Discharge current measurement test method
Figure 7: Discharge current measurement test method

 

The data was collected, and the average discharge current graphed with previous materials to determine the general ability of the material to limit discharge currents. The graph is shown below in Figure 8. It should be noted that the current is reported in milli-amperes on a LOG scale. The differences in the values on the vertical scale are significant. Homogeneous dissipative materials exhibited discharge currents approximately two orders of magnitude lower. These lower discharge currents are below Class 0 device failure thresholds. For instance, a MR tape head with a voltage threshold of 60 V had a corresponding current threshold of 100 mA. Manufacturing process requirements were set to limit discharge currents to 10 mA to prevent ESD damage. (See http://www.dangelmayer.com/class-0-case-studies.php.) Material A and Ceramic are the only two materials in Figure 8 that satisfied this criterion.

Figure 8: Voltage versus peak discharge current for various materials
Figure 8: Voltage versus peak discharge current for various materials

 

Conclusions

It is important to understand that current, not voltage, causes ESD damage to electronic devices, circuit boards and assemblies. Selection of handling and packaging materials that may come in contact with electronics must be both static dissipate and homogeneous to adequately limit discharge currents to prevent CDM or CBE ESD damage. Reliance on static dissipative SRM properties alone is not sufficient for Class 0. This has been repeatedly confirmed by laboratory test results, manufacturing data and numerous MR Head papers published at the EOS/ESD Symposium.

The MR tape head industry found the current liming properties of homogeneous ceramic tweezers (Figure 8) reliably prevented damage to tape heads with ESD failure thresholds between one and three volts. Therefore, selection of such materials would ensure tote boxes, handling and storage containers would prevent ESD damage during their use for all ESD sensitivities including Class 0. Material A and Ceramic are the only two materials in Figure 8 that satisfied this criterion.

Many materials used in the market today (most carbon-loaded polymers) do not adequately limit discharge currents to prevent CDM or CBE ESD damage. Material A in this article out performed all of the materials in this investigation including the ceramic tweezers that work so well for the tape head industry. It was consistently in the static dissipative range and exhibited lower discharge currents than ceramic tweezers up to 900 volts charging levels. These discharge currents were approximately two orders of magnitude better than carbon-loaded polymers and were below Class 0 device failure currents.

Endnotes

  1. A. Olney, B. Gifford, J. Guravage, A. Righter, “Real-World Printed Circuit Board Failures,” EOS/ESD Symposium Proceedings, EOS-25, pp. 34-43, 2003. 
  2. “EOS versus ESD Misdiagnosis: Charged-Board Events Are a Growing Industry Concern,” G. T. Dangelmayer, T. L. Welsher, and A. Olney, Medical Electronics Manufacturing, Spring 2009

 

author_newberg-carlCarl Newberg has a B.S degree in Metallurgical Engineering, a M.S. Degree in Materials Science, and a professional engineer’s license (Met. Eng.). He is also a iNARTE Certified ESD Engineer, and ESDA as a Certified ESD Program Manager. He has been a member of the ESD Association Board member, Standards Chairman, Technical and Administration (TAS) Committee, participated in standards working groups on ionization, packaging, clean rooms, garments and gloves. Carl was the Technical Program Committee Chairman for the 2004 EOS/ESD Symposium, Vice Chairman for the 2005 Symposium, and General Chairman for the 2006 Symposium. Carl is the President of MicroStat Laboratories/River’s Edge Technical Service, and can be reached at carl@dangelmayer.com.

 

author_dangelmayer-tedTed Dangelmayer, BSEE, is the president of Dangelmayer Associates, L.L.C. and has been developing ESD programs since 1978 for large global corporations as well as individual proprietorships. His accomplishments include President emeritus ESD Association, chairman of the ESD Association Standards Committee and Technical Program and General Chair of the EOS/ESD Symposium, President NE ESD Chapter, published numerous magazine articles, technical papers and two books, ESD PROGRAM MANAGEMENT, holds three patents, and is NARTE Certified ESD Engineer. Ted can be reached ted@dangelmayer.com.

 

Terry Welsher, PhD., is currently Senior Vice President of Dangelmayer Associates and was previously Director of the Quality, Test & author welsher-terryReliability Center at AT&T Bell Laboratories. His accomplishments include President emeritus ESD Association, chairman of the ESD Association Standards Committee and Technical Program and General Chair of the EOS/ESD Symposium. He also has served as member of the EOS/ESD Symposium and ESDA Boards of Directors, Board of Directors of JEDEC and has authored or co-authored of over 40 papers in solid state physics, applied mathematics, organic chemistry, electronics reliability and electrostatic discharge. Terry can be reached at terry@dangelmayer.com.

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