USB cable connections have become ubiquitous over the past decade, while the data rate keeps increasing. SuperSpeed USB host controller ICs are very sensitive to electrostatic discharges. Because the end user connects cables in non-electrostatic protected environments, system vendors require high levels of ESD robustness, typically up to 15kV contact discharge according to IEC 61000-4-2 [1].
Over the years, the speed requirements for the connections have steadily increased, up to 10 Gbps (USB3.1) and beyond (HDMI2.0). This implies that the system level protection should ensure not only a good ESD protection but a high signal integrity as well, which limits the available capacitance budget. Typically, a maximum capacitance of about 0.25 pF is assumed [2]. A further requirement is a very low clamping voltage of 7 V at 15 kV in order to allow protection of high-speed SoCs which do not allow a high isolating impedance between protection and SoC. This requires a low snapback voltage and limits the dynamical resistance of the protection to about 0.3 Ω.
This article describes the design of a stand-alone (off- chip) protection device which meets all requirements. The device concept is based on a Semiconductor Controlled Rectifier (SCR), which has been in use as ESD protection for a long time because of its superior ESD performance per area and low clamping voltage. Since the SCR typically has a high triggering voltage, some sort of low- voltage trigger must be added to allow triggering at sufficiently low voltages. The overall concept used is very similar to a Low-Voltage-Triggered SCR (LVTSCR) [3,4], except that the low-voltage triggering is not achieved by means of a ggMOST but by an avalanche diode. A cross-section of the device is shown in Figure 1 (top). A replacement diagram is shown in Figure 1 (bottom). In order to reduce the high trigger voltage Vt1, determined by the nwell and low-doped p-sub junction, an additional p-type trigger diffusion pt is added.
On-chip SCR IO protections have been reported over the past years, either optimized for low capacitance at typical HBM current levels [5], triggered by a diode string [6], or with ultra-fast triggering [7].
In order to meet the design parameters for the stand-alone system-level protection described in this article, in particular the combination of a high current capability (typically 30 A TLP) and an ultra-low capacitance (0.25 pF), a novel bipolar process technology was developed.
The process development was supported by an extensive simulation effort. A 2D TCAD simulation of the new technology was performed using TSuprem4 [8] and the electrical characteristics of the LVTSCR were simulated using Medici [9]. In order to simulate the triggering behavior of the device a 3D simulation was performed using Synopsys Sentaurus [10]. The simulations of the new technology are described in the following section (“Simulations”). Characterization data of the protection devices as well as application tests are given in the section “Characterization.”
Simulations
Since none of the available bipolar processes was capable of meeting the 15 kV/0.25 pF target, a novel bipolar process was developed based on an RF bipolar technology with double wells. In particular, the new process includes a low-doped substrate, optimized diffusion profiles and a new process back-end for minimum capacitance, as well as a low-capacitance trigger. A device cross-section is shown in Figure 1.
Simulated ESD performance
The SCR is built using a shallow p+ diffusion as anode in an n-well in a very low-doped p- substrate and a shallow n+ diffusion as cathode in a p-well. Both wells are connected to the terminals. The SCR has a multi-finger layout (Figure 2). The design is scalable. By increasing the number of fingers, the ESD performance can be increased accordingly. But at the same time, the junction capacitance will increase proportionally as well.
Due to the low-doped substrate, the SCR trigger voltage Vt1 is very high (~80 V). A separate p-type trigger diffusion pt is introduced to decrease the trigger voltage independently of the well diffusions. If the pt diffusion would surround the n-well completely, the junction capacitance would be too high, because of the higher pt concentration. In order to minimize this effect, the pt diffusion is not laid out all around the n-well but in stripes, as shown in Figure 2.
The width of the stripes is as small as possible (0.6 µm) to minimize the capacitance. Moreover, for the same reason the number of stripes should be as low as possible, without jeopardizing homogeneous current flow. Measurements of test structures with 1, 2, 4, and 8 strips show that even a single stripe allows a smooth triggering of the entire finger. Furthermore, failure analysis of the device after ESD discharges which exceed the ESD strength shows random filaments which are not related to the position of the trigger stripes.
For reverse polarity pulses the current path is through the integrated diode in the SCR structure (Figure 1).
Integrated SCR and diode
Transient mixed-mode device simulations with analytical diffusion profiles were performed in Medici to assess the expected ESD capability. The 15 kV ESD target translates into a 100 ns TLP second breakdown current It2 » 30 A [11]. The simulated TLP I-V curves showed a significant unbalance in the ESD capability via the SCR (Figure 3) and the return diode (Figure 4). The simulations were done on 2D SCR structures without pt trigger. Therefore, the trigger voltage is about 80 V. The x-axis in Figure 3 is cut at 20 V.
Whereas the SCR current path yields an It2 > 60 A, the diode path only shows approximately It2 » 25 A. The reason for this unbalance is the longer path of the charge carriers in the diode compared to the path in the SCR (Figure 5), because of the arrangement of the shallow (n+ and p+) diffusions.
Because of the longer current path, the voltage drop and, thus, the power dissipation is inherently higher in the diode, which yields a lower ESD capability.
The solution is simple and straightforward: Instead of mirroring the layout of each finger, each finger is copied by translation as many times as needed to obtain the overall target ESD capability [12]. Now current flow in the SCR and diode direction is separated in the silicon, whereas a single metal stack is used by both (Figure 6).
This results in a virtually identical ESD capability in both directions (Figure 7), while maintaining the low capacitance. Both polarities meet the 30 A target.
The simulations show, furthermore, a very low dynamic resistance in the silicon of only 0.1 Ω, which leaves about 0.2 Ω for the resistance of e.g. bondwires for a target spec of 0.3 Ω for the product, and allows to reach the 8 V clamping voltage limit at 30 A of TLP current.
Note that the SCR and diode I-V curves are very similar once the SCR has triggered, which reflects the near-identical current path in the SCR and diode direction. The voltage is slightly higher in the SCR direction, because the SCR needs some current to bias the wells in order to maintain SCR action.
Simulated Junction Capacitance
The target for the junction capacitance was set at Cj » 150 fF, in order to leave sufficient margin for the backend capacitance. Cj (1 MHz, 0 V bias) is obtained from an AC simulation in Medici. Results are shown in Figure 8.
Several factors contribute to the junction capacitance, most importantly the doping level of the substrate, which determines the depletion width (Figure 1). It was found that the substrate doping level must be below about 1e14 cm-3 in order to meet the 150 fF target. The junction capacitance scales with the square root of the p-sub concentration, as is expected due to the dependence of the depletion width on concentration. Of course, the distance between the wells must be sufficiently large to accommodate the resulting depletion width. Based on the simulations, it was decided to use a 200 Ωcm (7e13cm-3) substrate, which was regularly available for other process technologies.
Interface charge
The data in Figure 8 are valid for a situation in which the oxide charge is negligible. In real life, the amount of oxide charge is dependent on the oxide deposition process. Figure 9 shows the impact of the oxide charge on the junction capacitance.
The reason is that if the oxide charge exceeds a certain minimum level, an inversion layer is created in the lowly-doped p-substrate. In case of a substrate dope of 7e13 cm-3, an oxide charge of only 2e10 cm-2 is sufficient to create an inversion layer.
The inversion layer around the n-well effectively extends the n-type area in the p-type substrate (Figure 10), thus increasing the junction capacitance with increasing well spacing Wnp. This implies that the sum of the junction capacitance Cj (which decreases with Wnp) and the inversion layer charge Cinv has a minimum at a certain Wnp, in our case at Wnp ≈ 2.5 µm (Figure 11).
Process Backend Capacitance
In addition to the process front-end (FE), the process back-end (BE), including metallization and inter- metal dielectric, needs to optimized as well in order to avoid a large BE contribution to the overall device capacitance. The capacitance target for the BE is 30 fF which leaves sufficient capacitance budget (70 fF) for the package.
Figure 12 shows a typical stack for a 4-metal back-end. One significant contribution to the capacitance stems from the height H between anode bondpad and substrate. The second major contribution is given by the distance D between the metal stacks at anode and cathode potential.
Obviously, for a low bondpad capacitance, the dielectric height H must be as large as possible. But increasing H also increases the metal stack capacitance for a given distance D between the metal stacks.
The impact of H and D on capacitance has been estimated using a parallel plate approach. For this purpose, the capacitor between the metal stacks is approximated as continuous metal plates of height H and width W (total device width) at a distance D. The bondpad capacitance is approximated as a plate with the bondpad area at a distance H.
Increasing H is achieved by adding additional metal modules to the process. Versions with 2, 3, and 4 metals were compared. Table 1 shows that a 4-metal stack is needed to meet the 30 fF capacitance budget for the BE. A further optimization involves removal of the intermediate metals, which are not needed for routing, through which an additional 10 fF can be saved [13].
| 2 metals | 3 metals | 4 metals | |
| bondpad | 44 | 20 | 14 |
| metal stack | 6 | 10 | 13 |
| total | 50 | 30 | 27 |
Table 1: BE capacitance contribution in fF
Voltage Overshoot During Triggering
It is well-known [2,14] that, during the finite time it takes to build up sufficient charge to sustain the ESD current, a voltage overshoot is observed, which is dependent on the transit time of the carriers through the low-doped portion of the device, in this case the p-substrate. The overshoot voltage is an important design parameter. In our case, the small Wnp » 2.5 µm yields a very fast switch-on time of about 0.5 ns (Figure 13), less than the first IEC peak risetime. For comparison, a typical vf-TLP measurement is shown. There is very good agreement between simulation and measurement within the limited resolution of the vf-TLP.
The brief overshoot does not cause damage to the target circuits to be protected due to the on-chip protections which act as secondary protections which clamp the voltage.
Furthermore, a 3D (Sentaurus) simulation was used to assess the lateral spread of the current during the initial triggering phase. The 3D geometry is shown in Figure 14. A trigger diffusion, of 0.6 µm width (in the Z-direction), is introduced at the edge of the crystal (at position 0) and a transient mixed-mode simulation is started which represents a TLP pulse.
Figure 15 shows the simulated current profile. At 32 ps after triggering, the current is still localized in the trigger diffusion. After 150 ps the current already flows homogeneous within a factor of 2. The eventual current density (e.g., 3.4 ns) is lower, because the current now flows over the entire device width. This indicates that there is no danger of current crowding due to the trigger stripes, which is further confirmed by physical analysis of failed devices, which show random filaments, not related to the trigger stripes.
DC Breakdown Voltage
The trigger voltage depends mainly on the concentration of the pt trigger diffusion (Figure 2). The DC breakdown voltage BV was simulated as a function of pt trigger concentration in a DC Medici simulation. The result is shown in Figure 16. In order to avoid a high tunneling leakage, a BV = 8 V was chosen, which can be achieved by using a pt concentration of 3e18 cm-3.
Type Inversion
Due to the very low substrate concentration of 7e13 cm-3, which is only 3 orders of magnitude above intrinsic level, the effective concentration is very sensitive to tiny disturbances in the silicon. It is well-known that in CZ-grown silicon, oxygen thermal donor (OTD) generation may change the effective doping concentration. OTD formation is strongly dependent on temperature, particularly in the range 400-500°C [15]. The final anneal temperature is usually in this range. Furthermore, the presence of hydrogen is known to accelerate the process of thermal donor generation [16].
Depending on the amount of OTD formation, the substrate type may even change from p-type to n-type. Since the final oxygen concentration depends on the original amount of interstitial oxygen in the substrates and on the total thermal budget during processing, type inversion occurs at some depth below the silicon surface. The top layer is not affected due to the out-diffusion of the interstitial oxygen.
Such a buried n-layer was found to increase the leakage of the SCR by several decades. This can be explained by a punch-through mechanism from the n-well to the buried n-layer. This punch-through current can be simulated in Medici (Figure 17). If the depth of the buried n-layer increases, the voltage to produce leakage increases, as expected for a punch-through process.
For very small buried n-layer depths, the leakage increases to µA-level for very small voltages. For larger n-layer depths, the leakage current stays at the reference level of about 0.1 pA up to higher voltages.
Interestingly, a small amount of OTD formation may actually be beneficial in the design, because it raises the effective resistivity of the substrate, thus allowing a lower junction cap. But it is important to avoid type inversion. By carefully tuning the anneal temperature, type inversion can be prevented, thus ensuring a very low leakage current, below the 1 nA target, while at the same time decreasing the effective substrate doping, which reduces Cj.
Characterization
After the process was defined using Medici and Sentaurus device simulation, a multi-product wafer (MPW) was designed in order to test the process parameter settings and calibrate the TSuprem4 process model.
Using the calibrated process simulations, products of 10 kV, 15 kV, or 20 kV ESD strength were designed in standard packages, either wire-bonded or leadless Cu-pillar. The protections may either be uni-directional (single device) or bi-directional (two identical devices connected anti-series). Figure 18 shows two package types: A four-channel wire-bonded SOT1176 package and a single channel Cu-pillar bi-directional SOD962 package.
Electrical Characterization
The I-V curve of the devices was measured by means of DC I-V measurements. The capacitance was measured using an LCR tester. TLP tests and gun-testing according to IEC61000-4-2 were performed as well.
Furthermore, several RF characteristics were measured: S-parameter and eye diagram on a USB3.1 application board.
DC I-V curve
The DC I-V curve was measured using an Agilent HP4155C parameter analyzer. The I-V curve (measured under current control) shows several distinct features of the SCR.
The leakage current at 5 V is about 1 pA, well below the 1 nA target. The DC breakdown voltage measured at 1 mA is BV » 8.8 V, close to the 8 V target. Beyond 1 mA, the voltage rises due to the pt trigger resistance until the SCR triggers at Vt1 » 12.3 V.
After triggering, the voltage across the SCR drops to the holding voltage of Vhold » 1.25 V. When the current increases further, the voltage increases in accordance with the dynamical device resistance of about 0.3 Ω.
When the current is decreased again, the voltage stays at Vhold until the SCR switches off, once the holding current Ihold » 15 mA is reached. The I-V curve in Figure 19 is written with decreasing current, in order to show the proper holding current.
TLP I-V curve
The devices were tested using an HPPI 3010C TLP system with 100ns/10 ns pulses up to 30 A for both polarities (Figure 20). The dynamical resistance Rdyn » 0.3 Ω, which yields a clamping voltage at 8 kV gun test voltage of about 4 V and, in combination with the fast turn-on time, allows very good protection of sensitive USB3 ICs.
The device capacitance is measured at 1 MHz and 150 mV amplitude using an Agilent 4285A LCR- meter. Figure 21 shows the device capacitance of a 15 kV device as a function of bias voltage. Because the capacitance is dominated by the n-well/p-sub junction capacitance, the capacitance decreases with increasing bias. At 1.5 V, which is the average voltage for USB3 pulse trains, the capacitance is 0.28 pF.
For bi-directional devices, the capacitance is much lower: 0.13 pF. This is about half the unidirectional capacitance, because this arrangement corresponds to two unidirectional devices in series.
IEC61000-4-2 (gun) test
A Schlöder SESD 30000 gun was used to perform HMM testing [17] (10 discharges per voltage level). The failure criterion was a 10% change in the DC I-V curve, measured after each voltage level. By scaling the total finger width, any desired ESD strength can be achieved. Table 2 shows an overview of ESD performance of several bidirectional devices and their capacitance, tested at 500 V steps until failure occurred. The capacitance per unit ESD performance is 10 fF / kV and scales excellently with device width.
| target level | 10 kV | 15 kV | 20 kV |
| pass level | 11.0 kV | 17.0 kV | 22.0 kV |
| capacitance | 0.10 pF | 0.15 pF | 0.20 pF |
Table 2: Gun pass levels and cap for several products
RF Characterization
The first requirement of an ESD protection is, of course, to protect well. But an equally important property of the protection is its non-interference with high-speed signals, e.g., USB3.1. In order to verify this, insertion loss and eye diagram measurements were performed.
Insertion loss
The insertion loss was measured using a ZVA24 Rohde & Schwarz network analyzer (24 GHz). The 3 dB cut-off point of the differential insertion loss for a wire-bonded 6-channel device is about 10 GHz.
For products in a leadless package, the 3 dB-point is beyond 24 GHz (Figure 22). For good signal integrity, a low inductance is as important as a low capacitance. Leadless devices use Cu pillars instead of bondwires. Therefore, their inductance is much lower than in wire-bonded devices.
Eye diagram
Finally, the signal integrity was measured using a LeCroy WaveExpert 100 with a TDR step generator ST-20 and a CDR-E135 clock recovery module. Figure 23 shows an eye diagram for a USB3.1 pulse train via a testboard with a 4-channel protection device. The resulting signal integrity is excellent.
Application Tests
Application tests with the new line of protection products in combination with several popular USB3 SoCs were performed.
PUSB3FR4 / µPD720200
The PUSB3FR4 product is a 4-channel 15 kV protection. It is designed to protect both differential RX and TX USB3 channels, i.e. 4 lines. Application tests were performed using the PUSB3FR4 as protection and a Renesas µPD720200 USB3.0 host controller [18] as SoC to be protected. The RX differential pair is more sensitive than the TX pair, which contains additional 0.1 µF decoupling caps in the signal path. Table 3 presents an overview of the measured and simulated ESD performance of the RX IOs on a regular Renesas application board.
The columns labeled ‘meas’ have been measured using a Schlöder SESD 30000 gun. The columns labeled ‘sim’ have been simulated using a SEED model [11,19] and characterizing the SoC by means of TLP measurements.
Figure 24 shows the SEED model for the combination of Renesas SoC and PUSB3FR4 four- channel protection. R represents the trace resistance of about 1 Ω, taking into account the skin effect during a gun discharge.
The internal and external protections are modeled by piecewise linear Verilog-A models [11,19] which have been calibrated separately by means of TLP measurements. For the RX of the Renesas SoC (without external protection) a TLP failure current It2 » 3.2 A was found. Taking into account Von, Ron of both internal and external protections, measured by TLP as well, the total gun current to reach It2 » 3.2 A in the SoC with an external protection can be calculated by circuit simulation [20] in a straightforward manner. Conversion of the failure current into an effective gun voltage [11] yields the simulated voltages shown in Table 3.
| µPD720200 USB3 RX | Without protection | with PUSB3FR4 | ||
| sim | meas. | sim | meas | |
| pass pos | +1.6kV | >+2kV | +10kV | +10kV |
| pass neg | -1.6kV | -2kV | -11kV | -11kV |
Table 3: µPD720200 USB3 SoC and PUSB3FR4
Table 3 shows excellent agreement between SEED simulations and gun test results. Most importantly, it shows that the low inherent gun strength of the SoC alone is boosted to 10 kV by the PUSB3FR4 protection, before the leakage current increases.
PUSB3FR4 / Ivy Bridge Z77 Chipset
In another application test, the same PUSB3FR4 protection was used to protect the USB3.0 ports of an Intel Z77 PCI Express chipset BD82Z77 [21]. Figure 25 shows the positive and negative TLP curve for the USB3.0 port with (solid blue curves) and without (dashed black curves). Without protection the SoC internal protection dies at about 3.5 A. With PUSB3FR4 protection, no damage occurs up to the maximum TLP current of 10 A.
For positive voltages, snapback to 1.25 V is seen at 5 V. Because of the low-clamping voltage the SoC is well protected, both for positive as well as negative stress.
The combination of SoC and protection fails at It2 » 20 A for both polarities, when the residual current [19] into the SoC reaches 3.5 A. This corresponds to an ESD robustness of about 12 kV, similar to the previous example.
Other examples
Several other combinations have been successfully tested, including an AT1022 application board with an ASMedia 1142 USB3.1 host controller protected by a PUSB3FR4 up to 15 kV and the USB3 port as well as the HDMI2 signal pins of a Broadcom BCM7437 gateway SoC (for use in a set-top box) protected by a PESD5V0H1BSF bidirectional protection.
Summary
The development of a stand-alone (on-board) system level protection for high-speed cable connections has been described and successful operation demonstrated. The product family offers very low clamping voltage, sub-ns triggering and, hence, a very good protection. The signal integrity of high- speed communication lines, e.g., USB3 and HDMI2, is excellent. The insertion loss bandwidth is more than 10 GHz. The protection is shown to work very well with several popular USB3 chipsets.
Acknowledgement
The critical review of the manuscript by Javier Salcedo of Analog Devices Inc. is gratefully acknowledged.
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The paper on which this article is based was originally presented at the 36th Annual EOS/ESD Symposium in Tucson, AZ, and was given the award for the Symposium Outstanding Paper in 2015. It is reprinted here with permission from the ESD Association.
