Outstanding Paper at the 45th Annual EOS/ESD Symposium

Editor’s Note:  The paper on which this article is based was originally presented at the 44^th Annual EOS/ESD Symposium in September 2022. It was subsequently awarded the 2022 Symposium Outstanding Paper at the 45^th Annual EOS/ESD Symposium in October 2023. It is reprinted here with the gracious permission of the EOS/ESD Association, Inc.

Introduction

For high-speed interfaces and RF analog receiver circuits the total capacitive budget is very limited, to optimize performance the capacitance added by Electrostatic Discharge (ESD) protection must be minimized. For ESD protection design this means operating close to the victim breakdown. As the victims in these kinds of circuits are thin-gate oxides directly connected to the pad and the ESD robustness of the devices shrink with every technology node, the ESD protection becomes more challenging. The Charged Device Model (CDM) pulse with its fast and high currents is the most critical ESD event and to achieve “first-time-right” CDM robust designs, a predictive CDM simulation method for pre-silicon design is needed [1][6].

Existing methods of CDM simulation do not reliably predict the failure level of circuits with thin GOX gate at the pad. It was shown in [2] that for the GOX directly at pad the failure is caused by the initial fast current step of 20ps or less of the CDM event. It was also shown that the inductance of the critical path is very important for CDM performance. In another study [7], Charged Coupled (CC)-TLP, with pulse risetime of 20ps, has been demonstrated to predict CDM robustness reliably.

In this work, CDM simulation approach with stimulus current having initial risetime component of 20ps is investigated. The analysis is supported by CDM measurements of packaged Low Noise Amplifier (LNA) circuits, Very Fast (VF)-TLP measurements with 100ps risetime and ultrafast TLP (UF-TLP) measurements with 20ps risetime. To achieve a fast and simple simulation method the simulation is restricted to the receiver circuit itself and the complex RC network of charge distribution across the chip usual for CDM simulations are neglected and a simple charge distribution between VSS and VDD rail is assumed [3]. This is a valid assumption for designs using a common VSS rail for the IP block under investigation. Interconnect and device parasitics are considered by introducing parasitic resistance and inductance values to the schematic for CDM SPICE simulation. Resistance values are extracted. The initial range of inductance values are gained from layout assessment, which is refined based on the voltage measurements at the pads of reference structures. Capacitive coupling between metal lines is accessed to in range of femto-farad, the effects are considered negligible. The simulation is valuable both for an early design study with preliminary target values for resistance and inductance and for the final design using extracted values from layout. An excellent agreement of simulated and measured CDM failure thresholds for CDM currents could be proven for a large set of LNA test structures.

CDM Simulation Methodology

The following study is based on the set of test structures prepared for the purpose of optimizing a LNA receiver circuit. Since the CDM discharge nature is same for all the processes, these structures were used to prove CDM simulation methodology.

Investigated Devices

The devices investigated in this study consist of an input stage with thin-GOX MOS transistors tied directly or via cap to the pad, due to RF performance requirements. Dual diode protection, with small 6-finger diodes having fast turn-on time, is chosen as ESD protection. The supply filter and a large, dedicated power-clamp are placed close to the pad and routed well to avoid any inductive paths and to reduce bus resistance. The receiving gates are either directly connected to the pad or via a cap that is bypassed with a 200kΩ resistor to enable DC leakage testing to detect GOX damage. The discrete caps are placed at the critical path to the gate to capture the capacitive coupling effects. In total eleven different ESD protection topologies are investigated, out of which four circuit schematics (not showing supply-filter and power-clamp) are shown in Figure 1.

Each topology is a variant of “Basic.” “NoCap,” without capacitor and resistor in the RF line, connects GOX directly to pad. “2xAreaDiodes” has larger diodes (Y-size of active-diffusion increased to twice of Basic). “2xSecondStage” has second stage with twice the number of fingers as Basic. “NmosLkgOnly” has no resistor bypassing the cap in front of PMOS which allows detection of gate-oxide damage at NMOS. Table 1 summarizes the differences between the 11 ESD protection topologies.

Correlation of CDM with UF‑TLP

For silicon verification of the simulation results, test circuits were placed on a wafer-level chip scale package (WL-CSP) to perform CDM test, on an Orion 2 CDM tester with a JS-002 compliant test head. The damage was detected by a DC sweep between pad and VSS. Wafer-level packages resulted in negligible variation in peak currents during CDM [5]. The UF- TLP measurements were obtained by stressing the same receiver circuits on wafer-level. For analysis, both TLP positive stress and CDM negative stress produce positive current (positive charge flowing into the device). During CDM test procedure, 10 zaps were performed on a single device where the maximum of 10 measured peak currents, was used for analysis after DC readout. In CDM, lowest fail current and highest pass current out of 10 stressed samples were selected as First-Fail and Last-Pass, respectively, for the CDM degradation window of each test structure.

During a CDM event the sensitive gate oxide connected to the pad in an LNA circuit is damaged by the fast rise time component of 20ps or less as shown in [2]. VF-TLP with 1ns pulse width and 100ps rise time shows no correlation with CDM test (shown in Figure 2) and thus, cannot be used for predicting CDM robustness. Contrary to the expectation raised from the overestimation of the single LNA in [2], the CDM robustness can also be underestimated or show a “lucky” fit with the VF‑TLP results, depending on the circuit.

Ultrafast (UF-)TLP with a rise time of 20ps and pulse duration of 0.6ns is performed. The difference between VF- and UF-TLP is best visible in the comparison of current waveform and voltage response (shown in Figure 3 and Figure 4) where methods caused breakdown of the receiver gate. The fast risetime of the current pulse during UF-TLP stress leads to a significantly higher voltage overshoot measured at the pad because of the turn-on time (forward recovery time) of the diode protection. Comparing both current waveforms, the injected current with smaller magnitude and shorter pulse (UF-TLP) has damaged the victim GOX due to larger peak voltage.

Investigation of the same ESD protection circuits with UF-TLP shows better correlation, even though the UF-TLP underestimates the CDM robustness consistently by 0.5-1 A fail current, see Figure 5. This indicates that the rise time of the CDM pulse is slightly slower. In terms of the design robustness the worst-case assessment by UF-TLP is appropriate. With UF-TLP, the test structures have a range of fail currents because of the statistical nature of GOX breakdown.

Calibration of Schematic with TLP

To accurately model the circuits under a CDM event, we incorporated the parasitics of interconnect. Resistance of the primary ESD paths including branch-point resistance and resistance to the victim, were extracted using a PathFinder-based extraction tool [5]. The inductance of metallization was estimated using 0.3pH/µm rule on measured length of highest metallization from primary diodes to supply/ground bump [8]. Interconnect parasitics are shown as blue instances in Figure 6. Diode models were also improved for fast and large currents during CDM discharge by involving intrinsic resistance and forward recovery inductance of the diode. These were extracted from diode’s UF-TLP measurements and are shown as red instances in Figure 6. Intrinsic resistance is extracted from the ratio of quasi-static voltage to quasi-static current after diode turns-on during UF- TLP. Forward recovery inductance is extracted from the ratio of initial voltage overshoot to the rate of change of current (di/dt) during UF-TLP. These guidelines were used for modifying schematics, as shown in Figure 6, for all eleven ESD protection circuits.

Transient simulation was performed to check validity of interconnect parasitics and enhanced diode modelling. Rectangular current pulse, with 20ps risetime, was used as stimulus between RX pad and ground of the circuit “NoCap.” Shown in Figure 7, UF- TLP simulation and measurement results of “NoCap” are compared on a TLP IV plot which produced some surprising results. In this quasi-static region, the simulated voltage response fits well to the measured voltage response for different input currents. This validates resistive modelling and shows that the resistance extraction tool produced accurate path resistance values.

In Figure 8, a good match is shown between the simulated RX peak voltage and the measured pad peak voltage noted from voltage pulse corresponding to the UF-TLP current pulse at failure of the circuit. The vertical spread of blue inverted triangles corresponds to slight variation in failure currents due to statistical nature of GOX breakdown between samples. Simulation was performed with the measured failure currents and peak voltage plotted as red circle. The match between simulation and measurements provides confidence in the quality for the retrofit of the inductance values. Please note that due to topology of the presented circuits, significant amount of CDM current flows through the primary ESD stage so the peak voltage is dominated by its parasitics. This also indicates negligible contribution of the power clamp ESD path to the peak voltage at the pad.

CDM Simulation Setup

The fast rise time component in the CDM pulse originates from the initial spark discharge of the pogo pin stray capacitance and only contributes a part of the full peak current of the CDM pulse in the initial phase of the waveform, this has been proved by measurement and simulation in [2]. Distribution of the first 70% of the full CDM peak with 20ps rise time and the last 30% peak with a rise time of 100ps is chosen for the CDM simulation in this study as according to the CC-TLP study in [2], it predicts the failure of LNA circuit correctly.

The VSS network is relatively large, in terms of area, compared to the VDD network in our test structures. Considering the ratio, we assumed distribution of CDM relevant change of 10% on the VDD network and 90% of the charge on the VSS network. The CDM charge sources are simulated as current sources where the current source between pad and VSS rail contributes 90% of the current and the second current source between pad and supply rail adds 10% to the CDM current at the pad. The current waveform, shown in Figure 9, is used as current force into RX during transient analysis of circuit, as shown in Figure 6, in SPICE simulation. The maximum voltage across GOX of the victim from the voltage pulse in Figure 10, is compared it to the oxide breakdown voltage as the failure criteria.

CDM Simulation Results

For CDM simulation, different Ipeak current pulses, having same characteristics as shown in Figure 9, were generated and distributed between the VSS and the VDD net. Experimentally assessed P/NMOS GOX breakdown voltages, were used as a fitting-parameter (GOX breakdown uncertainty) to predict the breakdown current of the different LNA variants. The stronger victims with higher breakdown voltages, PMOS in CDM‑negative and NMOS in CDM-positive, were disregarded during evaluation. The voltage failure criterion is indicated by the dashed line in Figure 11b and corresponds to NMOS (inversion) in CDM-negative and PMOS (accumulation) in CDM- positive. For measured CDM currents, the legend is common between Figure 11a and Figure 11b. CDM simulation was performed with the recorded CDM-Pass and CDM-Fail peak currents which are shown in Figure 11a. For each case, the peak voltage across GOX is plotted in Figure 11b. These values have been normalized by the corresponding MOS GOX breakdown voltage. Figure 11b clearly shows that the method evaluates and differentiates between CDM-Pass and CDM-Fail based on GOX breakdown. The criterion is chosen to minimize the error in predicted pass-current of all investigated structures, shown in Figure 11a. Shown in Figure 11c, is the CDM prediction inaccuracy for each test-structure which has been calculated using the data from Figure 11a. The term Measured LastPass refers to the highest measured peak discharge current during CDM stress where the structure survived or did not show any degradation in the post-stress DC evaluation. CDM prediction average inaccuracy is ~10% for the negative and ~15% for the positive.

Summary

A novel CDM simulation approach involving current-force transient simulation with 20ps rise time component in the CDM current pulse has been shown to predict CDM failure. Initial 20ps rise time provides a much better prediction of the CDM failure level due to GOX breakdown of MOSFET device in the receiving circuit than the classical approach with assumption of a 100ps risetime pulse. The importance of interconnect parasitics and diode modelling during CDM simulations has also been highlighted. The methodology has been proven for a set of 11 ESD protection circuits, different topologies with gate-at-pad designs, in a state-of-art technology.

References

1. P. Tamminen, R. Fung, and R. Wong, “Charged device ESD threats with high-speed RF interfaces,” 2017 39th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), pp. 1-8, 2017.
2. D. Johnsson, K. Domanski, and H. Gossner, “Device Failure from the Initial Current Step of a CDM Discharge,” in Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Reno, 2018.
3. S. S. Poon, K. Sreedhar, C. Joshi, and M. Escalante, “A Full‑Chip
   ESD Simulation Flow,” in Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Reno, 2015.
4. A. Jahanzeb Y-Y. Lin, S. Marum, J. Schichl, and C. Duvvury, “CDM Peak Current Variations and Impact upon CDM Performance Thresholds,” Proc. EOS/ESD Symposium, pp. 283-288, 2007.
5. Ansys Pathfinder. https://www.ansys.com/products/semiconductors/ansys-pathfinder-sc
6. J. Willemen et al., “Characterization and Modeling of Transient Device Behavior under CDM ESD Stress,” Electrical Overstress/Electrostatic Discharge Symposium, Las Vegas, 2003.
7. J. Weber, R. Fung, R. Wong, H. Wolf, A. Horst Gieser, and L. Maurer, “Comparison of CDM and CC-TLP robustness for an ultra-high speed interface IC,” 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), pp. 1-9, 2018.
8. C. Russ et al., “Enablement, Evaluation and Extension of a CDM ESD Verification Tool for IC Level,” 43rd Annual EOS/ESD Symposium (EOS/ESD), 2021.