A Discussion on Low-Cost Printed Circuit Board Design

How to Handle Those Pesky Commodity Designs That Run the World

If you were to look at any electromagnetic compatibility (EMC) publication over the last few years and categorize their content to get a feel for the problems people in the industry face, one topic usually dominates the conversation. That topic? Simulating and characterizing high-speed interconnects on large stack-ups. The degree of freedom large stack-ups give designers is large as they usually offer at least one of each of the following, if not more:

• A solid power plane, used for distributing VCC throughout the board;
• A solid ground (return plane) throughout the board; and
• At least one layer through which you can route critical traces in absence of noisy ones that would otherwise cause signal integrity issues.

Smart routing and use of planes help with the radiated and conducted emissions coming from a board switching into the gigahertz range. To seasoned designers, Figure 1 demonstrates a routine stack-up.

However, this leaves untouched the large topic of commodity designs where single layers, wire jumpers, and sub one-dollar assemblies are not only necessary but mandatory when going into mass production and cost is critical. Examples of these devices include the human machine interfaces (HMI) on white goods which include stoves, washer/dryers, and microwaves. There was once a time where you could successfully have a mechanical engineer design/layout those boards while having that person be happily unaware of any EMC concerns. However, with the advent of connected devices, that is no longer the case.

This leads us to these designs being fundamentally more challenging. Instead of having four or more layers to help ease the burden of controlling electrical noise, the designer gets one (sometimes two) layer(s) to do all those things previously listed. And while signal integrity and gigabit interconnects aren’t normally an issue in these applications (yet), the following are examples of things that are:

• Communication bus integrity over a UART, I2C or SPI bus;
• Passing IEC 61000 series testing such as surge and conducted immunity/noise testing; and
• Getting more exotic technologies working such as capacitive touch HMIs or LCDs.

The lack of multiple layers to offer a low impedance path for any electrical disturbances, especially on boards with longer geometries such as the interface for your washing machine (illustrated in Figure 2), often results in the designer needing to carefully choose the acceptance criteria in their testing as it usually leads to having to account for degraded performance.

The successful design of a low-cost printed circuit board (PCB) starts after schematic/requirements are captured, and is a function of adopting a sound strategy for layout based on an understanding of what makes a return path a “good path.” This strategy requires an understanding of the different return path schemes commonly found on one- and two-layer low-cost assemblies. After that, we’ll discuss what types of plane layouts and connections are commonly found in low-cost designs. And finally, we will join these two topics together with an overall goal of introducing a design strategy to help you better plan your layout up front.

How Does a Return Path Affect Return Currents in Practice?

Like a house, any good printed circuit board (PCB) structure, no matter how simplistic or complicated, always starts with the foundation, (or in our case, the return path). We first visit this very popular subject by asking, what do we want in a good return path?

If you would ask a seasoned EMC engineer this question, they would respond with a low impedance (not necessarily resistance) path for currents to return to their source. We want to minimize impedances to both:

• Reduce loop areas, which will cut down on radiated emissions and conducted interference; and
• Minimize voltage differences between reference points.

A ground or reference plane is a fundamental tool in a PCB to achieve these goals, since they function to create a return path which references all points along that system to the same potential. In theory, all points are referenced at the same potential without voltage differences between them, with return currents taking the most direct path back. In practice, however, the inductance the current return loop creates will cause a varying impedance across the board, depending upon the path the return current takes. This problem is further exacerbated in more challenging designs where you need to share a plane with signal routing; an example of this is shown in Figure 3.

We explain this situation using the diagram of two concentric current loops, as shown in Figure 4.

Without considering the return path, the current will ideally always take the shortest (least resistive) path back to its source. However, if we include the mutual inductive coupling factor between the inner loop and the source loop (Figure 5), and simulate, we notice that the impedance of that inner loop decreases with frequency, resulting in the current taking the path closer to the source and resulting in a longer loop.

And while large loops can result in unwanted radiated emissions, another example can be found in amplifier circuits (Figure 6). Here, depending upon the variability, you could develop offsets at the input terminals, or these could create an unwanted phase shift resulting in stability issues.

These examples demonstrate why more experienced designers state that a good return path (or reference) works to tie a board together. However, in single and dual layer layouts, this is not always the case and we must identify situations where these unwanted impedances arising from non-contiguous planes may cause a problem.

And as such, it is not uncommon to find wire jumpers or 0 ohm resistors galvanically linking two different conductive sections of a return plane together in lower-cost designs, posing a problem in the return path. For example, if you were to compare the inductance of a solid copper plane to that of a 20 AWG wire, you would find a remarkable difference. This difference acts as an impedance that will affect current flow, as shown in Figure 7.

This situation would result in a larger return loop, in which higher frequency currents return through a different source elsewhere on the printed circuit board, and resulting in either an increase in emissions or unwanted interference.

From these examples emerge rules that form the basis of what makes a good return path. We notice that in each of these two examples common things appear, both related to current wanting to take the path of least impedance:

• The path of least impedance is usually the path that is closest to the signal trace at higher frequencies; and
• Circuit instability, or noise caused by voltage drops in conductors.

With respect to EMC and signal integrity, we want to work to control and minimize impedance between reference connections. These are usually (but not always) dominated by the physical length parameter, and as length increases so does inductance.

And as such, we develop rules so that when someone asks what makes a return path good we can qualitatively analyze it to deliver an answer. Rules for low-cost designs include:

• Try to not split planes, either power or return. If you find that split planes are necessary, do not route a signal across them; 
• Keep the return loop area small by trying to have as contiguous of a return plane as possible, this will minimize common mode emissions;
• If you have the choice of a power or return plane, choose the return plane; and
• When using strip line/single tracks to feed integrated circuit packages, use a gridded configuration.

Violating any one of these rules could either increase your risk for emissions, or cause impedance discontinuities leading to conducted emissions problems. Now that we have come up with some practical examples and rules to follow, let’s now consider at a few different strategies a layout engineer may use when designing their board.

Common Return Path Schemes

After understanding that return currents and impedances control the performance of not only your device but more importantly your circuit function when undergoing EMC testing, the next thing is to develop some strategies to use when going through a layout. Before placing their first component, it is important that engineers have a tool box from which to pull designs. While a solid copper plane should always be your first choice, these examples demonstrate that they may always not fit the application and they come in many different types. In general, reference systems can be split into the following categories:

• A single point return path (Figure 8) found on low-cost designs, focusing on DC power up to a few megahertz, after which the impedance brought on by the length of the wires causes appreciable voltage drops between connections; or
• A hybrid single point return path (Figure 9), in which sections of the circuit with a common function such as digital electronics or a MCU and oscillator are referenced together.

Usually you will find that each of these reference systems on a PCB are then tied off/connected to a chassis and that is used as the common reference for the system. The drawbacks to these systems are the length of each of your system’s components connections to a reference, and the length between their connections. An example of this is demonstrated in Figure 10.

In addition, as the lengths start to approach resonance with the parasitic capacitance, the connection makes to reference the circuits could create parallel impedances that can isolate different sections of the system from a common reference at certain frequencies.

In short, these types of reference systems are not suitable for assemblies that are long and rectangular in length, such as HMI boards that must fit a certain form factor. As the length approaches longer than a few inches, the inductance of the (return path) trace becomes an issue in controlling common mode currents.

A common improvement for a single-point reference scheme is a multipoint reference system (Figure 11). This is commonly found on layouts which require a high degree of RF performance at higher frequencies. These systems take the hybrid single-point scheme and improve upon it by making multiple connections, which are shorter than 10 percent of the wavelength of the highest frequency signal traveling on the conductor.

In addition, you may find more than one direct connection to a chassis or the use of capacitors to provide a low impedance for high frequency currents to travel back to the source.

The drawbacks in the multipoint reference system occur when:

• Since everything is referenced together, higher frequency currents traveling the chassis can result in a strong common mode current; or
• Depending upon the spacing between connection points, unintentional loops can be created which can result as a pickup for stray signals.

As a result, care must be taken when creating unintentional loops and using capacitors. For example, while many simply just add (or throw) capacitors at the problem until their emissions spikes go down, it is important to understand the resonance the capacitor value makes with the inductance could result in an unwanted impedance spike. This situation is demonstrated in Figure 12 where one tie-off point’s parasitics are modeled as a filter network.

While these types of reference systems can be found in any printed circuit board design, lower-cost designs are at higher risk for poor implementation and can result in time-consuming edits to the layout. Now that common types of reference systems have been discussed, we turn to some real-world examples of some assemblies as example case studies to aid in our understanding of a reference plane.

What Are The Different Types of Return Paths Found in Low-Cost Applications?

When implementing a low-cost design, it is likely that the designer will be faced with needing to use either traces or some sort of non-contiguous plane for a return path. This along with the usage of non-fiber-based dielectrics present a much lower manufacturing cost but a much larger problem from a functionality point of view. To lower the impedance for all return currents to reduce voltage differences at ICs references, some common design schemes are presented here from which a layout engineer may choose

A Single-Track Return Path

The first of these examples start with the basic concept of trying to have as many parallel paths for the current to take back to the source as possible on a single layer, thus lowering the overall resistance. For low-cost boards operating under a megahertz, you may reference paths are usually arranged as a multipoint grid. While designers should always strive for placing as much copper as possible, the component density could be so great that laying down a solid copper plane would result in too many islands or unconnected pieces of copper.

As a result, we usually find this structure when there are multiple packages to link together (Figure 13). When using this type of return path structure, it’s important to avoid long runs, because if the assumed track impedance to be given by (1), you can easily see that the longer the trace the more impedance it will have.

L_trace = .005(length)(ln(4/diameter)-.075) uH (1)

In addition, a thicker track is always preferred to a narrower one, especially if it’s a branch of a return path that holds return current for several packages.

A Single Copper Layer

A typical design methodology for adding a copper plane to a product is going through the steps of:

1. Laying out your critical components;
2. Stitching your critical signals together; and then
3. The void space left over from steps one and two can then be filled with copper and then tied to a common point resulting in the product’s reference plane.

There are several things to which you need to pay attention when following these steps. The most readily available process for a designer to undergo is to evaluate the density of components on their printed circuit board. What often ends up happening on tight single layer packages is that the components, along with their critical routes will cause copper to be left floating or unconnected. To help identify and eliminate these problems, layout software has implemented checks to remove unconnected pieces of copper.

After you’ve made a reasonable attempt at placing the components, a trick that you can try is to do a polygon pour with whatever layout software is being used, and look at the net connections and how that may segment the pour. You can easily undo this after you get a visual representation of the layout and adjust accordingly. If cost allows, you can often save space and help reduce EMC concerns by simplifying packages as follows:

• Reduce the number of transistor drivers with a single SPI/I2C driver integrated circuit; or
• Use an internal oscillator instead of external if your tolerances allow it.

However, if you’re unable to reduce the density of the components on the circuit board, you are often left with the next step, that is, using zero-ohm wires and thermal relief/pads connected to a copper screen.

Since the goal is to always try to implement the best return plane, for an application consisting of a single-sided PCB packed tightly with components, the only option is often limited to either:

• Use zero-ohm wires to connect different sections of the plane together, such as in a single-sided piece of copper with through hole components;
• Make trace paths etched out of a solid copper plane negative. Then, attach the packages to the copper plane at their eyelet, through hole, or relief points.

In the case of zero-ohm wires connecting difference pieces of return copper together, it’s important to remember that those connections are made at DC and the impedance of those (often) skinny zero-ohm wires is much higher than that of the copper plane. Figure 14 demonstrates a commonly-used technique where the layout engineer is encouraged to put stitching capacitors across the break in the plane to help with higher frequency decoupling.

In the case of trace paths being etched out of a copper plane, its usage falters again when the density of components becomes too great. While each circuit is referenced to the same plane, the fact the traces cut through the plane puts this configuration at risk of larger loop areas. An example of this strategy is shown in Figure 15, where the center of the board has effectively no copper to act as a plane due to trace spacing.

Ideally, if this type of assembly is desired, it is best to place your sensitive circuitry in the same vicinity and have as few traces as possible cutting through the plane near the return connections. This helps to ensure as small of an impedance discontinuity as possible between return connections.

While we have discussed multiple ways of less than perfect implementation of a return path on single-layer, low-cost boards, it is almost inevitable that we have a discussion on PCB rules and not find some sort of reference to breaks or cuts in a return plane. While the reasons against them are widely known, with the short answer being an increase in loop area of your return currents, the breaks aren’t always obvious. Discontinuities in the return path can be thought of as two distinct situations:

• A complete break in the return path; this is usually reserved only for very special cases such as galvanically isolating two parts of a circuit, is easy to spot and is often accompanied by some sort of optical isolation; or
• A partial break in the return path with large islands connected by narrow strips, which are often harder to spot but more prominent on densely-populated single and (sometimes) two-layer boards.

While breaks and long islands should be avoided, they are typically found with in-line IC packaging or PCB assemblies with mounting standoffs that exist in the center of the board. Examples of an example of a slit in the plane due to through-hole IC packing is shown in Figure 16.

If breaks are necessary, it should be standard practice to either keep all currents in a common section or use copper traces to:

• Link multiple copper islands together using a small piece of copper trace;
• Place a thin copper trace between in-line packaging through holes; or
• Use the breaks in the plane to your advantage and place sensitive parts of the circuit away from identified critical return paths.

Some of these techniques are shown in Figure 17.

Introducing a Return Path Strategy, and What to Look for in Design Reviews

Now we have a good overview of not only what makes up a good return path, but some examples of what they look like in low-cost systems that utilize a single layer. However, a question that has been frequently posed to me is how do you successfully analyze a system for a possible noise hazard before layout. While this may seem like an easy question to answer for those who have been in the industry, engineers new to complicated low-cost layouts may not be as savvy. For this reason, this article recommends that a designer put on their system engineering hat to better design and document their system. After all, a design is only as good as it’s understood and tested to.

This means that before sitting down to your favorite CAD software to start a layout, a designer must do one more thing, that is, partition their system according to their requirements and components, and not start by placing components haphazardly. While each engineer has their own method for doing this, it is important to have a method. This process isn’t too dissimilar from a software engineer’s UML diagrams which describe their software and is made up of a set of documents that describe each section of the design process.

A diagram of the system partition could either be a sketch or CAD file, and would represent the final product and where things could go in general. By doing this early in the design process:

• You can point out potential hazard points such as mounting hole issues; and
• Discover issues that may segment your return path, giving the layout engineer a head start on portioning their system.

By addressing the schematic and system requirements, the engineer doing the layout can zone off different sections of the board to get an idea of which groups of components will fit together. An example of a way of portioning a system is found in Figure 18.

Next, after giving an overview of how the system is to be partitioned, a return path map can be sketched out. This is described as a diagram that shows how each major section of the system (described in the previous paragraph) is referenced. An example diagram is shown in Figure 19.

By doing this you provide a simplified representation of your design to engineers, providing an at-a-glance- review of what parts of the section could be critical or at risk for crosstalk or interference. In addition, it is at this point you can begin to add specific requirements to each section of the circuit on this map, such as:

• Switching frequency.
• Sensor accuracy.
• Current carrying requirements.

By adding these onto the diagram in Figure 19, you can start to get a picture of a system where interactions between sections may exist, and if they’re likely to have a negative impact.

At this point, it’s important to note that in the documentation phase, the layout engineer has not referenced their electrical design (EDA) tool very much. Lastly, before your layout proceeds to a recommended practice for any integrated circuit or microcontroller, create a pinout list. This has both the added effect of being easily reviewable in case of a missed connection while also allowing the user to group different pins together. This is especially helpful in the case of a MCU where pins can often be multiplexed to keep critical signal traces, such as analog to digital signals, away from digital switching traces (SPI lines, or PWM drives). An example can be found in Figure 20.

By grouping functionality together and identifying early on if a trace is critical or if it needs external componentry the, layout engineer can often rotate or place the part in such a way as to minimize the amount of segmenting/routing.

With the system level diagram, the reference routing diagram, pinout and requirements in hand, the engineer has a set of documentation that can be easily understood by a group, providing a solid foundation upon which to build their design.

Conclusion

Low-cost designs are often an underserved and challenging part of any layout engineer’s career, especially as technology progresses and things like digital ICs, capacitive touch replace mechanical buttons, and high-speed communication interfaces become more ubiquitous. The ability for a design to offer a low impedance return path to reduce the costly possibility of failure at test time is dependent upon:

The ability to recognize what a good return path is and isn’t;

• Access to a toolbox from which to pull when designing into an assembly requires finesse; and
• The ability to properly document and plan a design to minimize movement of components and signal routing, thus increasing accuracy and reducing design time.

While these techniques and ideals are not specific to low-cost designs, they are certainly more critical when design constraints become tighter. And because low-cost designs are getting increasingly complicated, it’s important to pay attention to the fundamentals and ensure the integrity of your return path to produce a low-cost and worry-free design.

Christopher Semanson works at Renesas Electronics America Inc. as an Electrical Applications Engineer in Durham, NC supporting a wide variety of general purpose applications. He has five years previous experience in EMC Education at the University Of Michigan, teaching EMC and Electronics with Mark Steffka. He has a bachelor’s degree in Electrical and Computer Engineering and a master’s degree in Electrical Engineering from the University of Michigan Dearborn. Chris can be reached at christopher.semanson@renesas.com.