Artificial intelligence (AI) has emerged as a significant game-changer across various industries. This influence of AI has fueled a dramatic increase in silicon fabrication, leading to substantial advancements in the semiconductor industry.
One of the most notable advancements in silicon fabrication and manufacturing is the development of high bandwidth memory (HBM) stacks. This should not be confused with the human body model for electrostatic discharge (ESD) model. These memory die stacks, which are located near the processor, have been increasing in number. This proximity and increased die stacking enhance memory density and the speed and efficiency of data transfer, significantly improving the performance of electronic devices that utilize AI hardware algorithms.
One concern with multiple die stacking is the risk of ESD at the die-to-die (D2D) interface during the manufacturing process. Because of this, there is a requirement to balance the amount of ESD protection on the interface without interfering with the speed, silicon area, and design at the interface. Progressively, advances in the D2D interconnect are becoming smaller and denser, further limiting the amount of acceptable ESD protection.
Recognizing this challenge, the ESD industry council recently updated a whitepaper. [1] This whitepaper presents the charge device model (CDM) specifications and requirements specifically for D2D interfaces. Figure 1, taken directly from the whitepaper, details the future reduction of CDM targets as the density of the D2D interfaces continues to increase. This roadmap is critical for aligning manufacturing ESD levels with the ESD protection at the D2D interfaces.
The increasing number of die stacks presents an additional challenge: the potential for cumulative ESD damage. Figure 2 demonstrates that with multiple die stacks, a repetitive ESD event could occur and propagate through the die interconnect with each die placement.
This repetitive stress, even within the “acceptable” D2D voltages suggested by the white paper, could lead to ESD damage. This damage could be observed with degradation in oxides based on the time dependent dielectric breakdown (TDDB) or with other time-to-fail ESD methods. [2] [3] [4]
The very-fast transmission line pulse (vfTLP) is an ESD tool that we can use to evaluate key elements for on-chip ESD design. With a constant 1ns pulse width at a set voltage, we can increase the number of stresses from a single pulse to a larger stress number to observe the impact of cumulative stresses. Figure 3 demonstrates measured data, showing the reduced performance of stress across a gate oxide and the reduced performance also for the fusing capabilities of metal interconnects.
In conclusion, as with all on-chip ESD designs, there is a delicate balance to maintain. This balance is between supporting the minimum amount of ESD protection to prevent damage during manufacturing and avoiding ESD over-protection, which could lead to speed and silicon area limitations. The white paper provided by the ESD council helps align this balance. However, due to the innovative advancements of the D2D interfaces, special circumstances may need to be considered.
References
- Industry Council on ESD Target Levels, “White Paper 2: A case for lowering Component-level CDM ESD Specifications and Requirements Part II: Die-to-Die Interfaces,” August 2023.
- S. Oh, et al., “An Analysis of CDM-induced BTI-like Degradation using VF-TLP in Advanced FinFET Technology,” 2024 IEEE International Reliability Physics Symposium (IRPS), Grapevine, TX, USA, 2024, pp. 1-5.
- C. Troussier, et al., “Estimation of Oxide Breakdown Voltage During a CDM Event Using Very Fast Transmission Line Pulse and Transmission Line Pulse Measurements,” 2021 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2021, pp. 1-5.
- A. Ille et al., “Reliability aspects of gate oxide under ESD pulse stress,” 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Anaheim, CA, USA, 2007, pp. 6A.1‑1-6A.1-10.
