Just as Intel co-founder Gordon Moore predicted back in 1965, engineers have continued to double the number of transistors per square inch on integrated circuits every two years. This miniaturization of chips makes technology faster, smaller, and cheaper—but it also poses a challenge for engineers who need to measure the chips for design and testing. Researchers from the National Institute of Standards and Technology (NIST) and Intel are now using a new X-ray scattering technique to accurately measure features on a silicon chip to within fractions of a nanometer, or about the width of a single silicon atom.
New measurement tools are critical for the semiconductor industry. Today’s chips are so small that features such as lines, trenches, holes on silicon slices now measure just single-digit nanometers. Integrated circuits now squeeze several billion transistors on a slice of silicon smaller than a postage stamp. Adding to the shrinking size, chip architecture also continues to get more complex, with FinFET transistors being introduced in 2011, and now 3D stacked transistors being developed.
The new measurement technique, called CDSAXS (critical-dimension small angle X-ray scattering), takes advantage of the short wavelength of X-rays and their sensitivity to differing densities of electrons in the materials they hit. This has an advantage over current measurement tools, which rely on visible and ultraviolet light with wavelengths much larger than the features being measured. Small angle X-ray scattering, on the other hand, operates at a wavelength less than 0.1 nanometer, which is small enough to capture even the tiniest details on modern chips.
Early results of NIST’s state-of-the-art CDSAXS measurements of these nanometer-sized structures have provided very useful atomic scale resolution of their 3D profiles.
