A featured Year-In-Review (YIR) presentation was given at the recent 2019 EOS/ESD Symposium by Alan Righter, new president of the EOS/ESD Association, entitled “Commonalities and Robustness of ESD and EMC Tests”. The motivation and abstract for this YIR talk was to highlight in what ways ESD and EMI/EMC co-exist and various ways they are considered/used together in analysis of ICs and systems.
It is known that ESD events generate EMI, which can cause damage in devices beyond the ESD event itself. Much work has been in process to better understand the relationship between different ESD tests and EMI/EMC, including how EMC-centric tests such as transient and surge extend the realm of understanding effects on ESD devices and systems (boards). One example is ongoing work highlighting the use of the IEC 61000-4-2 test, different results between IEC guns and IEC pulsers, use on ICs versus systems, and improving IEC 61000-4-2 waveform description/characterization. This YIR considered seven topics illustrated by recent works in journals and ESD/EMC related conferences, each of which focused on a particular topic.
The first topic, ESD events generating detectable EMI in Manufacturing, was illustrated by a paper from Maloney [1]. He described an apparatus and model for measuring EMI generated from Charged Device Model (CDM) events in automated manufacturing. Destructive CDM electrostatic discharge events can happen in semiconductor manufacturing and they are shown to be detectable from radiation that results from collapse of an electric dipole. The analytically describable radiation field pulse of CDM (fully developed in the paper) was shown to be readily produced with a new instrument (CDM Event Simulator or CDMES) that creates dipole collapse at will. A coaxial monopole E-field antenna’s transfer function was shown to capture the particular energy spectrum of the antenna signal in near-field, and experiments in the factory were shown to compare well with these models.
The second topic, Commonalities of ESD and EMC Tests, was illustrated by a paper from Righter [2]. Components and systems must be qualified in terms of a set of electrical robustness characteristics. The various test methods of ESD and EMC (component level HBM and CDM, IEC 61000-4-2 System Level ESD, -4-4 (Electrical Fast Transient, -4-5 (Surge); ISO 10605 (Automotive System Level), and ISO 7637-2 and -3 (load dump and fast/slow transients) were described and were related in terms of their application to various electronic entities, certain robustness environments and energy profiles, and transport/interaction with electronics. Figure 1 shows an example from the paper of charge multiples of common automotive transients and how they map to a power vs. time profile for an LDMOS.
The third topic reviewed was ESD Protection Impact on EMC Performance. Abouda et al. [3] considered system-level stresses such as EMC stress (Direct Power Injection, Bulk Current Injection, and Radiated Field) and presented two case studies where ESD protection impacted the conducted emission (CE 150ohm: first case study) and the conducted immunity (DPI: second case study) performance. Examples were given of ESD gun stress directly applied to ICs with no external protections. Failure mechanisms are explained and design optimizations fixing EMC issues (as measured) were presented. The ESD strategy/ESD protection architecture for a particular pin architecture was found to significantly impact EMC performance. Simulation of functional performances during EMC and ESD events remains very challenging for analog products over the frequency domain, regarding high injection mechanisms.
The fourth paper reviewed, covering the topic of Issues with EMC injection during System Level ESD, was from Patnaik et al. [4]. This paper described a human-assisting robot created by the author team and consisting of many subsystems such as sensors, display, motors, and control, to assess impact of ESD on subsystems. Figure 2 shows the schematic/model of the robot. ESD events were analyzed beginning at the robot tribo-charging point extending through the sensor disruption. The idea behind this analysis is that the EMI field couples into system wires, leading to noise injection and subsequently soft errors. Based on the robot’s acquired charge voltage, the discharge current was simulated using a simple switch model along with the loop impedance limiting the current. Discharge current coupling to the sensor was described using S-parameters with equations obtaining the noise voltage at the sensor. The noise voltage from the event is compared to the sensor’s calculated and simulated noise sensitivity threshold to reproduce the disruptive event. The simulation model could help system designers assess ESD risks and help to efficiently design filtering networks.
The fifth paper reviewed, covering Modeling of Different ESD and EMC Events, was from Leveugle and Weyl [5]. This paper presented a novel methodology to develop and validate disturbance generator models creating a virtual EMC lab. New simulation models for ESD, EFT and Surge stimuli were created and verified on a wide range of load conditions. An example of two different models for the IEC 61000-4-2 pulse and measurement/simulation results are shown in Figure 3.
The sixth paper, covering the topic of Understanding System Level ESD Performance of TVS Diodes, was from Yoshida and Endo [6]. In the paper they postulated that protection performance of an ESD device at the component level changes when the device is implemented in a circuit at a system level. Additionally, the operating characteristics/protection performance of an ESD-protection device were postulated to differ from device to device even if the protection device specifications are the same. To show this, an evaluation/simulation method was developed expressing realistic differences in the ESD-protection-performance of devices relying on TVS diodes. Protection characteristics of TVS diodes were evaluated with a vector network analyzer, where four types of TVS diodes having very similar specifications were measured and compared. The described evaluation/simulation method was shown to express the differences between the four similar TVS diodes in terms of the attenuation of the pass frequency responses (as measured with s-parameters). In addition, the reproducibility of the measurement for different PCB patterns was also confirmed. Figure 4 shows two plots from the four TVS devices in this paper showing the frequency response variability.
The final work, covering Issues with System Level ESD Testing of Components, was from Muhonen [7]. This Invited Talk from the 2019 International ESD Workshop described the pitfalls of component-level testing using the IEC 61000-4-2 system level test standard. While components such as ICs are not completed systems, OEMs still ask their vendors regularly to test components by themselves according to this standard. However, there is no real guidance for this in the IEC 61000-4-2 standard itself, and the component-level test results have been shown to have varying degrees of repeatability depending on the type of component tested.
This talk reviewed several controlled experiments from two round robin test procedures (as part of the EOS/ESD Association Human Metal Model WG5.6 Working Group) to determine the amount of variability that is typical in this type of test. Similarities and differences between testing to the IEC 61000-4-2 standard and the HMM standard practice were also described. Based on these WG5.6 Round Robin results, and spectral analysis of different guns/pulsers used in these tests (shown in Figure 5), guidance and recommendations are given to those who have to conduct the test regardless.
Further work on the ESD/EMC relationship for different stresses is in progress and planned to be presented at upcoming EMC and EOS/ESD Symposiums.
References
- T. Maloney, “The Case for Measurement and Analysis of ESD Fields in Semiconductor Manufacturing,” 2018 IEEE Symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity (EMC, SI & PI).
- A.Righter, “Relating the Commonalities and Robustness Characteristics of EMC and ESD Tests,” 2018 IEEE Symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity (EMC, SI & PI).
- K. Abouda, P. Besse and E. Rolland, “Impact of ESD Strategy on EMC Performances – Conducted Emission and DPI Immunity,” EMC Compo 2011 – 8th Workshop on Electromagnetic Compatibility of Integrated Circuits, November 6-9, Dubrovnik, Croatia.
- A. Patnaik, W. Zhang, R. Hua, L. Chuang, A. Huang, H. Lin , B-C. Tseng, and D. Pommerenke, “Systematic Evaluation of Soft Failures in System-Level ESD Transient Events,” IEEE Trans. On Electromagnetic Compatibility, Vol. 60, No. 5, Oct. 2018.
- C. Leveugle and T. Weyl, “Implementation Methodology of Industrial and Automotive ESD, EFT and Surge Generator Models which Predict EMC Robustness on ICs and Systems,” 2017 EOS/ESD Symposium Proceedings.
- T. Yoshida and M. Endo, “A Study on ESD Protection Characteristic Difference By Measurement of TVS Diodes by VNA,” 2017 IEEE Symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity (EMC, SI & PI).
- K. Muhonen, “System Level Testing of Components,” IEW 2019 Invited Talk Presentation.
Alan Righter is currently a Senior Staff ESD Engineer in the Corporate ESD Department at Analog Devices. He works with ADI design/product engineering teams worldwide on whole chip ESD planning/design, ESD testing, ESD failure analysis, and EOS/EIPD issues with internal and external customers. Alan has held various executive positions within the EOS/ESD Association and is now president for 2010-2021.
