Design

This article describes a laboratory experiment that shows the impact of the decoupling capacitors and a PCB trace length on the signal integrity in a CMOS inverter circuit.

This column outlines the steps to consider when embedding ESD detection capabilities into your system and overall design flow.

The trend of progressively migrating both ESD and EMC immunity from the system/board to the component level is creating unprecedented challenges for the component ESD designer.

Occasionally, we are asked to help develop shielding effective for near-field low-frequency (LF) magnetic fields, perhaps in a situation where some regulatory agency has imposed limits on LF magnetic field emissions of our product, and we are forced to comply.

The narrow ESD design window in current FinFET technologies creates a special challenge for the robust ESD design of high-speed interfaces. Smart circuit-ESD co-design can help achieve the required ESD robustness without deteriorating functional performance.

Although understanding each capacitor type and behavior is daunting and difficult to memorize, it is prudent that every aspiring engineer and technician involved in design for EMC at least have a rudimentary understanding of what capacitor technologies are available.

This article offers some useful insights and guidelines on how to effectively design and test systems using wide band gap devices to optimize product performance and achieve EMC compliance.

This article describes a practical way to improve signal integrity of typical interfaces on the PCB when using external ESD devices.

In this article, we describe how wireless measurements of human body voltage can be made, and why they are important for ESD managers.

This updated version of an article originally published in the March 2014 issue provides details on recent and current developments in the ESD testing of electronic products.