Pin Holes & Staples Lead to Diminished Performance in Metallized Static Shielding Bags

As early as 1985, the author recalls re-occurring discussions of the effects of puncture holes from component leads and stapling of static shielding bags.

In July 2013, the ESD Experts page on LinkedIn® started a discussion by a USA computer manufacturing company that generated participation from end users, suppliers and consultants both here and abroad. In years past, some held opinions that pin holes do not greatly affect static shielding of metallized bags. There is, however, minimal published data to fall back upon regarding this subject matter.

One major factor influencing Type III (Mil-PRF-81705E) or a Level 3 (ANSI/ESD S11.4) ESD shielding bag constitutes fracturing of its thin metallized vacuum deposited layer. Excessive wear and pin holes from leads of circuit cards pose risks. The size and magnitude of the pin holes determine bag attenuation from a high voltage discharge. In Figure 1, left, the reader will observe through hole (“thru-hole”) components and a single microscopic puncture to the right.

Figure 1

In this article, the author will not address Type I, Level 1 & 2 Aluminum Moisture Barrier Bags (MBB). ANSI/ESD S541-2008 (Packaging Materials for ESD Sensitive Items), ANSI/ESD S11.4-2012 (Static Control Bags Standard) and Mil-PRF-81705E-2010 (performance specification for ESD bag films) reference ANSI/ESD STM11.31 testing for static shielding bags. The current release of ANSI/ESD S541 designates ESD bag shielding at <50nJ. Aerospace & Defense follow Mil-PRF-81705E with a limit of 10nJ max. Consequently, ANSI/ESD S11.31 (Figure 2) was used by the author to determine the effects of pin hole damage with Type III or Level 3 metallized shielding bags.

Figure 2

This article specifically illustrates the differences in shielding bag performance due to pin holes and stapling. Conditioning took place at 12.3%RH, 73.4°F for 48 hours. Note: ANSI/ESD STM11.31 testing is conducted at 12% & 50%RH after 48 hours of preconditioning for qualification.

In Figure 3, left, one can observe a staple affixed to a shielding bag; the photograph to the right represents 3 puncture holes in another ESD bag. Each bag was subjected to six (6) discharges at 1KV. A new bag free from pin holes, staples or blemishes produced a series of waveforms as illustrated in Figure 4 and Table 1.

Figure 3

Figure 4

Table 1: 12.3%RH, 73.4°F after 48 hours

Initial testing of a brand new electrostatic discharge shielding bag (Type III) measured 13nj which is under the limit (<20nJ) set by ANSI/ESD S11.4. However, these shielding results still fall short of the Mil-PRF-81705E requirement of 10nJ max.

A single staple did impact a new bag’s shielding performance from approximately 13nJ to 19nJ (Figure 5). Additional staples would pose a greater problem. In like manner, 20 pin holes were created by pushing an ESD device through a new bag (Figure 6) leading to results in excess of <20nJ. This finding is significant since pin holes caused the bag to fail at 28nJ. The findings for each bag can be viewed in Table 2. The size of the holes did vary from bag to bag.

Figure 5

Figure 6

Table 2 (click image for larger view)

In summary, it is clearly evident by conducting the ANSI/ESD STM11.31 testing for electrostatic discharge attenuation that ESD bags with pin holes pose risks both inside and outside of an ESD Protected Area (EPA). Reliance upon data avoids speculation and warrants further study by the Author on ESD bag longevity in a manufacturing and distribution environment. Other risks include pin holes that will allow moisture pick up to take place, insects to enter, dust to infiltrate a package to compromise cleanliness in addition to contamination of the printed circuit board.

References

• ANSI/ESD S541, ESD Packaging & Materials Standard
• ANSI/ESD S11.4 (Static Shielding Bag Standard)
• Mil-PRF-81705E (DOD bag Performance Specifications)
• Following ESD Materials Validation Process, Controlled Environments, Bob Vermillion, August 26, 2010
• An US Army DAC Study, March 2012, Vermillion and White
• ESD from A to Z, Second Edition, Kolyer & Watson, Chapman & Hall, 1996
• Humidity & Temperature Effects on Surface Resistivity, John Kolyer and Ronald Rushworth, Evaluation Engineering, October 1990, pp. 106-110
• Packaging’s Fight Against ESD (RFID), Medical Device-network.com, March 2010, Doug Smith and Bob Vermillion

BOB VERMILLION, CPP/FELLOW Certified ESD & Product Safety Engineer-iNARTE is a subject matter expert in ESD mitigation of materials and packaging and is an ESDA Standards Committee Member. In 2010, Bob was the first to present on suspect counterfeit ESD packaging in the supply chain at the NASA-QLF. RMV is located on-site at NASA-Ames Research Center and is a NASA Industry Partner. Bob publishes numerous articles and white papers on advanced materials, packaging non-compliance and suspect counterfeiting in manufacturing, materials handling, shipping and long-term storage for the aerospace/defense, medical and electronics sectors. Speaking engagements include invitations from the DOD, DOE and NASA to present on supplier Iisues with materials and packaging. RMV is a NASA approved ESD laboratory at NASA-Ames. An internationally recognized author and inventor, Bob develops professional level ESD packaging seminars for Cal Poly, SJSU, UC Berkeley, Loyola Marymount, Clemson University and Oxford University. RMV is a 3rd Party ESD material testing, training and consulting company. Bob Vermillion is an active member of SAE G-19 Counterfeit Components and SAE G-21Counterfeit Materiel Committees. Bob can be reached at 650-964-4792 or email Bob at bob@esdrmv.com.